Memory access address comparison

Details Memory access address comparison Memory access address comparison

2000-05-02

2003-08-26

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S152000, C711S150000, C365S230050, C365S189040

Reexamination Certificate

active

06611904

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory system.
BACKGROUND OF THE INVENTION
Reference will first be made to
FIG. 1
which schematically shows a known memory system
2
. The known memory system
2
comprises a memory matrix
4
made up of a plurality of registers (not shown). Each of these registers is made up of a plurality of memory cells. The matrix
4
has four write ports
6
which can be used to write data to the registers of the matrix
4
. The matrix
4
also has eight ports
8
from which data can be read. With four writing ports
6
, care must be taken to ensure that two or more of the writing ports do not attempt to write to the same register at the same time. To avoid this problem in the known memory system, write protection circuitry
10
is provided.
The write protection circuitry
10
is connected to the output of an address decoder unit
12
which decodes the addresses to which each of the write ports
6
is to write. The write protection circuitry
10
compares the addresses decoded by the address decoder unit
12
and is able to identify if two or more ports
6
are to write to the same register. The output of the write protection circuitry
10
provides a write enable signal for each of the registers for each of the write ports
6
. If two or more write ports
6
are addressing the same location, only one of those write ports
6
will be able to write data to its given address. The other ports
6
would be deactivated. The output of the write protection circuitry
10
is connected to the input of a latch
14
which also receives a clock signal which controls the synchronization of the write enable signals applied to the matrix. The latch is transparent when the clock is low and locked when the clock is high.
After the latch
14
, the write enable signal is input to a NAND gate
15
along with the clock signal CLK in order to disactivate the write enable signals when the clock is low. The system of
FIG. 1
is such that the writing operation can be carried out only when the clock is high since the write enable signals are active only at this time.
The arrangement shown in
FIG. 1
is disadvantageous in that the provision of the write protection circuitry
10
upstream of the latch
14
means that unnecessary delay may be introduced, even when write protection is not required. Transitory states at the outputs of the latches may also cause the wrong output to be provided as a write enable signal.
Reference is now made to
FIG. 2
which shows a known memory cell which can be used in the memory matrix shown in FIG.
1
. The known memory cell comprises first and second pass gates
50
and
52
respectively. Each of the pass gates
50
and
52
comprises a first p-type transistor
54
and
56
respectively and a second n-type transistor
58
and
60
respectively. The gate of the p-type transistor
54
of the first pass gate
50
receives an inverse of a write enable control signal whilst the gate of the n-type transistor
58
of that pass gate receives the write enable control signal. Likewise, the gate
68
of the p-type transistor
56
of the second pass gate
52
receives an inverse of read enable control signal whilst gate
70
of the n-type transistor
60
receives the read enable control signal. Thus, the transistors of each pass gate
50
and
52
will either both be on when the respective control signal is high (i.e. active) or both be off when the respective control signal is low (i.e. disabled).
Connected between the first and second pass gates
50
and
52
is a latch
72
comprising first and second inverters
74
and
76
respectively. One end
78
of the latch
72
is connected directly to the first pass gate
50
whilst the other end
80
of the latch
72
is connected to the second pass gate
52
via an inverter
82
. One of the inverters
76
of the latch
72
is a tristate inverter and receives the write enable control signal as a controlled input. The tristate inverter
76
is off when the write enable command is high. When the pass gate
50
is on, the voltage at point
78
is forced only by the pass gate
50
and not by the inverter
76
. By using the tristate inverter, conflicts between the inverter and the pass gate
50
at the beginning of a write cycle are suppressed.
The known memory cell has a number of disadvantages. Firstly, the cell is relatively large. This is because the pass gates include p-type transistors which are relatively large compared to n-type transistors. Secondly, the memory cell requires four control lines; the write enable control line; the inverse of the write enable control line; the read enable control line; and the inverse of the read enable control line. This increases the size of the memory matrix as a whole and, in practice, it can be difficult to accommodate all of the required control lines. Additionally, there can be a problem with capacitance during the write command. The additional capacitance is caused by the tristate inverters. A write enable command sees the capacitance of the pass gates, of two transistors (one n-transistor, one p-transistor) for each of the tristate inverters and the capacitance of the line joining all these points.
SUMMARY OF THE INVENTION
It is an aim of embodiments of the present invention to provide write protection circuitry which addresses the problems of the prior art.
According to one aspect of the present invention, there is provided a memory system comprising a memory array having a plurality of memory locations; a plurality of write ports for writing to said memory array; write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, said write protection circuitry providing write enable signal for each write port, said write enable signals being applied to said memory array; and circuitry for controlling the timing of the application of the write enable signals to said memory array, said circuitry for controlling said timing being upstream of said write protection circuitry.
As a circuitry for controlling the timing of the application of the write enable signals is upstream of the write protection circuitry, there would be no effect on the performance of the memory system if write protection is not required. By providing the write protection before the latches as in the prior art, unnecessary delays occur even when write protection is not needed. This loss of timing is prevented by embodiments of the invention where the write protection is downstream of the latches. It is preferred that the output of the write protection circuitry be directly applied to the memory array. Putting the write protection circuitry as the last stage before the memory array protects the circuit from any transitory state at the outputs of the latches. Since it is the ultimate combination of the write enable signals which controls the writing operation, the protection is effective.
The write protection circuitry may be arranged to assign a hierarchy to said write ports. For example, n write ports may be provided and the first write port may have priority over the remaining n−1 ports and the nth port may have the lowest priority.
The write enable signals output by the write protection circuitry may be low when active and high when disabled. In other embodiments of the invention, the write enable signals may be high when active and low when disabled. The write enable signals are preferably always deactivated for one half of the clock cycle. This means delays will only occur if write protection is needed. When write protection is not needed, no electrical transition resulting in a delay occurs in the write protection circuitry. The number of write enable signals may be equal to the number of write ports multiplied by the number of memory locations. The write protection circuitry may be arranged to receive a plurality of signals indicative of the address of at least one memory location. These signals may be high when active and low when disabled.
The number of addresses may be equal to the number of port

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