MOS transistor with double drain structure for suppressing...

Details MOS transistor with double drain structure for suppressing... MOS transistor with double drain structure for suppressing...

1999-02-19

2003-07-22

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S917000

Reexamination Certificate

active

06597038

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a MOS transistor, and more particularly to a structure of a MOS transistor exhibiting an enhanced current drive capability while maintaining a high resistance to hot carriers.
2. Description of the Related Art
In recent years, various kinds of problems originating from the generation of hot carriers are being revealed accompanying the advances in fine patterning of the MOS transistor. This is caused by the circumstance that despite the reduction in the gate length of the MOS transistor as a result of fine patterning, its operating voltage is not lowered in proportion to the reduction in the gate length.
As a technique of realizing fine patterning without deteriorating the characteristics of the MOS transistor there has been known the scaling rule. This is a technique by which circuit parameters, such as the power supply voltage, are reduced in proportion to the reduction in the gate length. Thus, according to the scaling rule, when the channel length L is reduced to 1/k of its value, for example, the power supply voltage is also reduced to 1/k of the original value in the same manner as for the channel length. In practice, however, the MOS transistor is operated without reducing the power supply voltage to 1/k as required by the scaling rule. The reasons for the negligence of the rule are due to disadvantages that a satisfactory improvement effect of circuit characteristics cannot be obtained when the MOS transistor is operated at a low power supply voltage according to the scaling rule, and that it requires the supply of such a low power supply voltage from the outside. For these reasons, in the actual integrated circuits, MOS transistors are being used with reduced channel length but without corresponding change in the power supply voltage.
When fine patterning of the MOS transistor is promoted without lowering the power supply voltage, as in the above, the internal electric field of the MOS transistor is increased all the more. The internal electric field of the MOS transistor shows a maximum value in the vicinity of the drain, and impact ionization takes place in that region. Carriers gaining high energy generated by this phenomenon are referred to as hot carriers.
These hot carriers cause a variety of problems which harm the reliability of the MOS transistor. For example, traps and surface levels may be created by the implantation of the hot carriers into the gate oxide film, and the characteristics of the MOS transistor will be changed by the capture of the hot carriers by the traps and surface levels. As a result, a change in the threshold voltage and reduction in the transconductance gm will be brought about. Under these circumstances, various MOS transistor structures have been proposed in order to suppress the generation of the hot carriers which cause these problems. The doubly diffused drain (DDD) structure and the lightly doped drain (LDD) are examples of them. Both of the MOS transistors with DDD structure and LDD structure are structures provided with a lightly doped impurity region in parts close to the channel region of the drain region intended for relaxation of the electric field intensity.
The MOS transistor with DDD structure and the MOS transistor with LDD structure will now be described in the following.
First, the structure and the fabrication method of the MOS transistor with DDD structure will be described. FIG.
10
(
a
) through FIG.
11
(
b
) are sectional views showing the fabrication method of the MOS transistor with DDD structure arranged in the order of processes.
First, as shown in FIG.
10
(
a
), an element isolation insulating film
52
is formed by a selective oxidation method on the surface of a p-type semiconductor substrate
51
. Then, a gate oxide film
53
is formed by subjecting the sample to a thermal oxidation.
Next, as shown in FIG.
10
(
b
), a gate electrode
54
is formed on the gate oxide film
53
.
Then, as shown in FIG.
10
(
c
), a first n-type impurity, phosphorus
55
, is implanted into the p-type semiconductor substrate
51
by ion implantation. By so doing, a first n-type impurity layer
55
a
is formed in self-alignment with the gate electrode
54
. In this case, the ion implantation energy is 20-30 keV, and the dose of the ions is 1×10
14
to 5×10
14
cm
−2
Further, as shown in FIG.
11
(
a
), a second n-type impurity, arsenic
54
, is implanted into the p-type semiconductor substrate
51
by ion implantation. By so doing, a second n-type impurity layer
56
a
is formed in selfalignment with the gate electrode
54
. In this case, the ion implantation energy is 30-50 keV, and the dose is 1×10
15
to 5×10
15
cm
−2
.
Next, after forming a layer insulating film
60
on the entire surface and forming a contact hole, phosphorus
55
and arsenic
56
implanted in the p-type semiconductor substrate are thermally diffused by subjecting the sample to a heat treatment. In this case, since an impurity with a large diffusion coefficient diffuses to a wider area than an impurity with a small diffusion coefficient does, phosphorus having a larger diffusion coefficient compared with arsenic diffuses over a wider area. Because of this, as shown in FIG.
11
(
b
), there is obtained a structure (DDD structure) in which the impurity layer containing phosphorus with larger diffusion coefficient surrounds the periphery of the impurity layer containing arsenic with smaller diffusion coefficient.
Next, the structure and a method of fabrication of a MOS transistor with LDD structure will be described. FIG.
12
(
a
) through FIG.
13
(
c
) are sectional views showing the fabrication method of a MOS transistor with LDD structure arranged in the order of fabrication processes.
As shown in FIG.
12
(
a
), an element isolation film
72
is formed on the surface of a p-type semiconductor substrate by selective oxidation. Then, a gate oxide film
73
is formed by subjecting the sample to a thermal oxidation.
Next, as shown in FIG.
12
(
b
), a gate electrode
74
is formed on the gate oxide film
73
.
Then, as shown in FIG.
12
(
c
), a first n-type impurity, phosphorus
75
, is implanted into the p-type semiconductor substrate
71
by ion implantation. By so doing, a first n-type impurity layer
75
a
is formed in self-alignment with the gate electrode
74
. In this case, the ion implantation energy is 20-30 keV, and the dose is 5×10
12
to 5×10
13
cm
−2
.
Then, as shown in FIG.
13
(
a
), a sidewall insulating film
77
is formed on the sidewall of the gate electrode
74
. This sidewall insulating film
77
is obtained by forming an insulating film such as silicon oxide film on the principal surface of the semiconductor substrate using CVD or the like, then removing the component corresponding to the thickness of the formed insulating film by an isotropic etching.
Next, as shown in FIG.
13
(
b
), a second n-type impurity, arsenic
76
, is implanted into the p-type semiconductor substrate
71
. By so doing, a second n-type impurity layer
76
a
is formed in self-alignment with the gate electrode
74
and the sidewall insulating film
77
. In this case, the ion implantation energy is 30-50 keV, and the dose is 1×10
15
to 5×10
15
cm
−2
.
Next, as shown in FIG.
13
(
c
), after forming a layer insulating film
80
on the entire surface and forming a contact hole or the like, a metallic wiring
84
is formed selectively, completing a MOS transistor with LDD structure. However, the MOS transistor with DDD structure has a problem in that it tends to give rise to the short channel effect. As is well known, the short channel effect is a phenomenon in which a depletion layer extending from the source-drain diffused layer affects the depletion layer extending from the MOS surface to reduce the effective impurity concentration of the substrate. This effect gives rise to various kinds of problems related directly to the abnormality or reduction in the reliability of the circuit operat

Affiliated with

Also associated with

Rating

MOS transistor with double drain structure for suppressing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS transistor with double drain structure for suppressing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS transistor with double drain structure for suppressing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3074968