SOI device with metal source/drain and method of fabrication

Details SOI device with metal source/drain and method of fabrication SOI device with metal source/drain and method of fabrication

2002-01-11

2003-04-29

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S407000, C257S369000, C257S412000

Reexamination Certificate

active

06555879

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a semiconductor device having a metal source and drain.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. For example, in SOI devices with a thin body (e.g., about 15 nm or less), parasitic resistance can impede device operation. In addition, certain materials selected to be used in such a device may react with other materials when a thermal budget for the materials is exceeded (for example and depending on the material, when an anneal cycle approaches about 1000° C.).
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that optimize scale and performance. There also exists a need for corresponding fabrication techniques to make those semiconductor devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a MOSFET including a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the source and the drain and on top of an insulating layer, the insulating layer formed on a substrate; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.
According to another aspect of the invention, a method of fabricating a MOSFET comprising providing a wafer including a layer of semiconductor material having a thickness of less than about 15 nm and formed on a layer of insulating material, the layer of insulating material formed on a substrate; forming a layer of high-K dielectric material over the layer of semiconductor material; forming a gate electrode over the layer of high-K material; removing a portion of the layer of high-K dielectric material extending laterally beyond the gate electrode; and siliciding the layer of semiconductor material to form a metal containing source and a metal containing drain, thereby forming a semiconductor body therebetween having a channel defined by the gate electrode.


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patent: 6395589 (2002-05-01), Yu
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