Programmable ASIC

Details Programmable ASIC Programmable ASIC

1999-12-16

2003-07-01

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06588006

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing generic applications in an application specific integrated circuit (ASIC) generally and, more particularly, to using a programmable context switching state machine and register file to implement a programmable ASIC.
BACKGROUND OF THE INVENTION
Field Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) use programmable interconnects to program a desired function. State machines implemented in RAM or ROM have been used to represent simulation results.
Implementing programmable interconnects can constrain the chip size since the interconnects (i) consume much larger die area for equivalent gates compared to an ASIC, (ii) consume higher power since the interconnect typically has heavily loaded nets, and (iii) incur a higher cost. ROM state machines are constrained to a fixed address space and fixed output width, limiting usefulness to a small number of states.
SUMMARY OF THE INVENTION
The present invention concerns a method and/or software for programming a circuit comprising the steps of (A) simulating one or more states, (B) building program information in response to said simulation and (C) extracting from said simulation one or more unique states having current state to next state sequences.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) provide ASICs that may be manufactured at prices competitive with programmable logic solutions, (ii) enable flash memory use that will provide easier boot programming and line buffer miss programming, as well as accommodate larger designs of memories, (iii) allow L2 (Level 2) memory as an option to be fast embedded, providing a wide DRAM, (iv) implement a scalable architecture for small to large cores for standard parts, (v) be implemented in next generation process technology that will enable faster content addressable memory system (CAMS), more process blocks per chip I/O and faster chip I/O functions, and larger and faster embedded RAM, (vi) provide data paths that may be handled by register files, (vii) implement CAM technology with logic that may enable multiple process blocks to use the same entry signals, (viii) extract and process information from simulations to build a program image for a programmable ASIC, (ix) enable optimization of state minimization, (x) partition the states from simulation into process blocks for inputs and internal state sets, (xi) introduce copies of states to multiple process blocks or states to consolidate other states for a process block, (xii) fragment process blocks to pages, (xiii) optionally fragment pages such that input changes are not implemented, (xxv) enable a CAM that may be permanent (e.g., a CAM-ROM), (xv) reduce memory requirements and/or (xvi) reduce power consumption.


REFERENCES:
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5386132 (1995-01-01), Wong
patent: 5388266 (1995-02-01), Frey et al.
patent: 5568641 (1996-10-01), Nelson et al.
patent: 5585745 (1996-12-01), Simmons et al.
patent: 5600790 (1997-02-01), Barnstijn et al.
patent: 5706473 (1998-01-01), Yu et al.
patent: 5781769 (1998-07-01), Weber

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