Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-11-10
2003-09-09
Fahmy, Wael (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S239000, C438S243000, C438S253000, C438S386000, C438S396000, C438S660000, C438S650000
Reexamination Certificate
active
06617248
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor assembly, and more particularly to a method for forming layer of ruthenium metal.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor devices such as dynamic random access memories (DRAMs), microprocessors, and logic devices, several conductive structures are commonly formed. For example, transistor gates and capacitor bottom (storage) and top plates, typically manufactured from doped polysilicon, and interconnects and runners, typically formed from aluminum and/or copper, are formed on various types of devices.
A conductive material which has been used for various semiconductor device structures such as capacitor plates in ferroelectric devices is ruthenium oxide (RuO
2
). Ruthenium oxide exhibits good step coverage and a uniform thickness across various topographies. However, RuO
2
is not stable and is a strong oxidizer. It will, over time, oxidize various metal layers that are in close proximity. For example, if RuO
2
is used as a capacitor bottom plate, it will oxidize a titanium nitride or tungsten nitride top plate through a tantalum pentoxide (Ta
2
O
5
) capacitor dielectric. Further, a barrier layer must be formed to protect a polysilicon contact pad from the RuO
2
, as the RuO
2
will oxidize the polysilicon and result in a bottom plate being electrically isolated from the contact pad by a silicon dioxide layer.
Attempts have also been made to use ruthenium metal as capacitor plates or as various other structures, as ruthenium metal is stable and is easily planarized during chemical mechanical polishing (CMP). However, methods for forming a ruthenium metal layer, for example using chemical vapor deposition (CVD), result in a layer which has poor step coverage and has a rough surface. Ruthenium metal is formed excessively thin over features with excessive slope changes, and it does not adequately form in narrow areas such as deep digit line contact openings in a manner adequate to maintain its conductive integrity.
A method for forming a uniform ruthenium metal layer across severe topographies and which forms within deep, narrow openings would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method that reduces problems associated with the manufacture of semiconductor devices, particularly problems in forming a ruthenium metal layer. In accordance with one embodiment of the invention a ruthenium precursor and oxygen are introduced into a chamber to form a ruthenium oxide layer. Next, the ruthenium oxide layer is heated in the presence of a hydrogen-rich gas to convert the ruthenium oxide layer to a ruthenium metal layer.
As will be discussed, the uniformity of the completed ruthenium metal layer is significantly dependent on the flow rate of oxygen introduced with the ruthenium precursor. As the flow rate of oxygen is increased from a minimum to form the ruthenium oxide layer, the uniformity of the completed ruthenium metal layer increases. As the oxygen flow rate increases past a critical point, however, the uniformity of the completed ruthenium metal layer begins to deteriorate.
While it is believed that a uniform ruthenium metal layer formed in accordance with various described embodiments is most desirable, a less than uniform ruthenium metal layer formed in accordance with the descriptions herein may also have utility.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
REFERENCES:
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patent: 6278152 (2001-08-01), Hieda et al.
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patent: 2001/0043453 (2001-11-01), Narwankar et al.
patent: 2002/0037630 (2002-03-01), Agarwal et al.
“In-situ Barrier Formation for High Reliable W/Barrier/poly-Si Gate Using Denudation of WNxon Polycrystalline Si”, Byung Hak Lee et al., R & D Division, LG Semicon Co. Ltd., 1 Hyangjeong-dong, Cheongju-si, 361-480, Korea, 9/98.
“Tungsten Gate Structure Formed by Reduced Temperature Conversion of Tungsten Nitride”, C. J. Galewski et al., Genus Inc.
Copending Application: “Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers,” Vishnu K. Agarwal, et al., Ser. No. 09/590,795, filed Jun. 8, 2000.
Fahmy Wael
Martin Kevin D.
Pham Thanhha
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