Lateral double diffused MOS transistor

Details Lateral double diffused MOS transistor Lateral double diffused MOS transistor

2002-01-04

2003-05-06

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S335000, C257S336000, C257S344000, C257S396000

Reexamination Certificate

active

06559504

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, further detailedly relates to lateral double diffused (LD) MOS transistor technique as a high-voltage device utilized for IC for driving a liquid crystal for example and others.
2. Description of the Related Art
LD MOS transistor structure means structure that a new diffused region is formed by diffusing impurities different in a conductive type in a diffused region formed on the side of the surface of a semiconductor substrate and difference in diffusion in a lateral direction between these diffused regions is utilized for effective channel length and a device having the structure is a device suitable for reducing ON-state resistance because a short channel is formed.
FIG. 15
is a sectional view for explaining a conventional type LD MOS transistor and for an example, N-channel LD MOS transistor structure is shown. The description of P-channel LD MOS transistor structure is omitted, however, both structures are different only in a conductive type and it is well-known that they are the similar structure.
As shown in
FIG. 15
, a reference number
51
denotes one conductive type of, for example, P-type semiconductor substrate,
52
denotes an N-type well region, an LP layer
53
(composing a P-type body region) is formed in the N-type well region
52
, an N-type diffused region
54
is formed in the LP layer
53
and an N-type diffused region
56
is formed in an LN layer
55
(composing a drift region) in the N-type well region
52
. A local oxide film
57
and a gate electrode
59
via a gate insulating film
58
are formed on the surface of the substrate and a channel region
60
is formed in the superficial region of the LP layer
53
immediately under the gate electrode
59
.
The N-type diffused region
54
functions as a source region and the N-type diffused region
56
functions as a drain region. Also, a reference number
61
denotes a P-type layer for applying electric potential to the LP layer
53
and
62
denotes a layer insulation film.
In the LD MOS transistor, the dopant density of the surface of the semiconductor substrate (the LN layer
55
) is increased by diffusing the dopant into the surface to form the LN layer
55
as a drift region, current on the surface of the LN layer
55
readily flows and the withstand voltage can be increased.
However, as shown in
FIG. 15
, the end of the LP layer
53
to be a P-type body region of the LD MOS transistor is under the gate electrode
59
and a range in which the threshold voltage can be regulated exists under an active region.
Therefore, electrostatic focusing at the end of the LP layer
53
and the effect of an electric field from the gate electrode
59
are joined, local current focusing is caused and the driving ability is deteriorated.
Also, as high voltage is applied between the N-type diffused region
56
to be a drain region and the gate electrode
59
, the gate insulating film
58
is required to be thickened for high withstand voltage and it prevents further miniaturization.
FIG. 16
is a sectional view for explaining the basic configuration of a conventional semiconductor device.
As seen from
FIG. 16
, an isolation film (not shown) and a first and a second insulating gate
152
and
153
are formed on a semiconductor substrate
151
of a first conduction type, e.g. P-type. A gate electrode
154
is patterned to extend from the first gate insulating film
152
onto a part of the second gate insulating film
153
. Lightly-doped source/drain regions
155
and highly-doped source/drain regions
156
constitute a LDD (Lightly Doped Drain) structure. For brevity of illustration, only the side of the drain region is shown. A source/drain electrode is kept in contact with the source/drain region
156
.
Meanwhile, the locations of the density of an electric field at each voltage Vgs of the above semiconductor device through device simulation have been found by the inventors of this invention. It have been found out that the semiconductor device exhibits different breakdown voltage characteristics according to the distribution of the impurity density of the lightly-doped source/drain region
155
. Specifically, as seen from FIGS.
17
(
a
) and
17
(
b
), where the surface density of the source/drain region is relatively low (e.g. about 5×10
16
/cm
3
), the substrate current Isub have two peaks (double hump structure) as the voltage Vgs increases (FIG.
17
(
a
)). Incidentally, FIG.
17
(
a
) is a characteristic graph (Vds=60 V) showing the substrate current Isub versus the voltage Vgs at the above density. FIG.
17
(
b
) is a characteristic graph of the current Ids versus the voltage Vds.
First, the first peak (1) of the substrate current Isub shown in FIG.
17
(
a
) occurs owing to generation of an electric field from the drain region
155
toward the gate electrode
154
when the voltage Vgs<the voltage Vds. The electric field is concentrated at the first region (1) in FIG.
16
.
When the voltage Vgs=the voltage Vds, the potential difference between the drain region
155
and the gate electrode
154
disappears so that substrate Isub becomes minimum.
When the voltage Vgs>the voltage Vds, the resistance of the first region (1) shown in
FIG. 16
due to induction of carriers by the voltage Vgs is small whereas application of a voltage to the depletion layer in the second region (2) in
FIG. 16
is large due to resistance division. As a result, the electric field in the second region (2) in
FIG. 16
is dominant. Thus, the substrate current Isub increases again to provide its second peak (2) shown in FIG.
17
(
a
).
In this way, where the surface density of the lightly-doped source/drain region
155
is lower, the first peak (1) is low. Therefore, this is efficient for the drain breakdown voltage in the range where the voltage Vgs is low. However, the second peak (2) of the substrate Isub is relatively high so that the drain breakdown voltage cannot be maintained in the range where the voltage Vgs is high.
On the other hand, where the surface density of the source/drain region
155
is relatively high (e.g. about 1×10
17
/cm
3
), as seen from FIG.
18
(
a
), the substrate current Isub has a single peak at a certain Vgs. However, the drain breakdown voltage cannot be maintained in the range where the voltage Vgs is low. Incidentally, FIG.
18
(
a
) is a characteristic graph (Vds=60 V) showing the substrate current Isub versus the voltage Vgs at the above density. FIG.
18
(
b
) is a characteristic graph of the current Ids versus the voltage Vds.
Accordingly, where the lightly-doped source/drain region
155
is relatively low, the breakdown voltage in the range where the voltage Vgs is high cannot be maintained (region (I) in FIG.
17
(
b
)). On the other hand, where the lightly-doped source/drain region
155
is relatively high, the breakdown voltage in the range where the voltage Vgs cannot be maintained (range (II) in FIG.
18
(
b
)).
In order to relax the density of the electric field in the high voltage MOS transistor structure (N-channel), the end of the lightly-doped source/drain region
155
was retracted from the end of the second gate insulating film
153
by about 2 &mgr;m (removal width H), thereby realizing a high breakdown voltage of about 80 V. This is because the drain voltage is trapped at the portion of the removal width H because of an increased parastic resistance at this portion so that the electric filed applied to the transistor body can be increased, thereby realizing a high breakdown voltage of the transistor.
However, the process for realizing the breakdown voltage of 95 V which is being developed involves a further increased electric field as compared with the above process for realizing the breakdown voltage of 80 V so that the end of the lightly-doped source/drain region
155
must be further retracted from the end of the second gate insulating film
153
.
In this case, the increase of the removal width H lead

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