Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-11-23
2003-03-18
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S105000, C711S106000
Reexamination Certificate
active
06535956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of cache memory. More particularly, the present invention relates to a mechanism for detecting what type of cache is implemented within a computer system.
2. Description of Art Related to the Invention
For many years, computer systems have been designed according to a standard architecture. This architecture includes a central processing unit (“CPU”), main memory, cache memory element, a system controller controlling data transfers to cache memory via a cache interface and interface logic which allows the computer system to receive information from external sources such as IDE hard drives, keyboards and the like. Well known in the art, “cache” is relatively small, fast memory, usually static random access memory (“SRAM”), in close proximity to the CPU. Cache memory stores copies of the contents of frequently used memory locations within main memory in order to accelerate computations by reducing the number of accesses to main memory.
Currently, there are two types of cache memory both of which are based on SRAM technology; namely, pipelined burst cache and asynchronous cache. Although these cache memories are widely used in electronic systems, pipelined burst cache has been more frequently implemented by computer manufacturers and/or highly technical computer users over the last few years. The reason is that pipelined burst cache is able to support burst cycles thereby providing faster data access than the asynchronous cache.
Typically, cache memory is implemented onto a “Cache On A Stick” (“COAST”) module which is hardwired to a PC board. The COAST module is hardwired to the PC board because a Basic Input/Output System (“BIOS”), controlling the computer system during initialization, requires information as to which kind of cache is implemented within the computer system. Moreover, the reason for using the COAST module is to allow cache memory to be upgraded more easily without undergoing extensive modification the PC board.
In light of the continual advances in technology, it is contemplated that new types of cache memory, particularly pipelined burst cache, will be developed. One possible new type of cache memory, hereinafter referred to as “Mcache”, includes dynamic random access memory (“DRAM”) which requires refresh signals to avoid data loss. However, in the conventional cache interface, there does not exist any mechanism to detect whether conventional pipelined burst cache, Mcache or any other possible types of cache memory is implemented within the computer system. This leads to a number of disadvantages which effect both computer users and computer manufacturers alike.
One disadvantage is that the lack of any detect mechanism precludes computer users from upgrading their cache memories without overcoming a number of difficulties. For example, computer users would be required to know which type of cache is supported by his or her computer system prior to upgrading his or her cache. Moreover, the computer user would be required to reconfigure software, reset jumpers and perform other technical operations.
Another disadvantage effects the computer manufacturers by imposing further design constraints. With the emergence of multiple types of cache memory, the computer manufacturers would now be required to be even more cognizant of what type of cache is selected to populate computer boards for specific product lines to satisfy consumer needs. This further reduces design flexibility.
Thus, it would be advantageous to create a cache interface which can automatically discern what type of cache memory is implemented within the computer system to overcome those disadvantages cited above.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a mechanism to automatically detect whether cache memory is implemented with a selected type of cache memory different than conventional cache. The mechanism utilizes a unique interface including at least one cache detection signal line. The cache detection signal line propagates a cache detection signal from a cache memory element to a system controller. The cache detection signal is sampled after System Reset to determine whether the selected type of cache memory is implemented within the cache memory element.
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Dodd James M.
Langendorf Brian K.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Thai Tuan V.
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