Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-08-27
2003-04-29
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S055000, C327S067000, C327S534000
Reexamination Certificate
active
06556068
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuitry and in particular the present invention relates to compensation circuits for transistor threshold voltages in integrated circuits.
BACKGROUND OF THE INVENTION
Transistors, such as n-channel Field Effect Transistors (FET), formed in a Complementary-Metal-Oxide-Silicon (CMOS) integrated circuit operate when an input voltage is applied to a gate electrode. This gate voltage establishes an electric field perpendicular to a channel between a source and drain of the transistor. A conductance of the channel is controlled by the electric field. If no gate voltage is applied, a path between the source and drain is formed as two back-to-back pn junctions, and a drain current (I
D
) will be negligible. When a positive voltage is applied to the gate of the transistor, electrons are attracted to the channel. When the gate voltage exceeds a threshold level (V
t
), an inversion layer is formed in the channel to couple the source and drain. The threshold voltage level of a transistor is dependant upon several variables, both controllable and uncontrollable.
Relatively large threshold voltage variations from 0.4 to 0.6 Volts are common in current CMOS technology. This voltage variation is not compatible with lower power supply voltages implemented as the fabrication technology is scaled down to smaller dimensions. Power supply voltages of around one volt, or less, are required in integrated circuits fabricated with 0.1 micron CMOS technology. The statistical fluctuation of dopant atom concentrations in such sub-Micron fabrication can be significant and contribute to threshold voltage fluctuations.
Different techniques have been described for self-compensation of threshold voltages in nMOS technology by applying a negative substrate bias. One technique, which can be applied in CMOS technology to compensate for V
t
fluctuation, includes a capacitor connected to the transistor gate which is charged to correct the threshold voltage variations. This circuit is illustrated in
FIG. 1. A
current source
10
is coupled to both the drain
12
and gate
14
(through switch
20
) of the nMOSFET
16
. A reference potential is coupled to the gate through a large capacitor
18
and switch
22
. The capacitor is charged to a voltage required to maintain the current from the current source. This capacitor charge is retained while switches
20
and
22
are open and the transistor is connected only to the input signal at node
24
. This charge must be refreshed periodically since it can leak away as leakage current in the transistor switches. Threshold voltage variations are thus compensated for by the charge temporarily stored on the capacitor. This technique is practical only for a few critical transistors in an integrated circuit because of the size of the capacitor required for each compensated transistor, such as transistors in a dynamic random access memory device (DRAM) sense amplifier. This capacitor can be implemented in DRAM technology using a stacked storage capacitor.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a transistor threshold voltage compensation circuit for low voltage integrated circuits which is not dependant upon the provision of a gate bias capacitor.
SUMMARY OF THE INVENTION
The above mentioned problems with transistor threshold compensation circuits and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A threshold compensation circuit is described which generates a compensation voltage by regulating a backgate voltage of a transistor.
In particular, the present invention describes a threshold voltage compensation circuit for providing a compensation voltage. The compensation circuit comprises an n-channel transistor having a gate, drain and source fabricated in an isolated p-type well, a current source coupled to the drain and the p-type well, and a voltage supply for coupling the gate to a reference supply. The compensation voltage is provided at the drain for coupling to additional transistors. In an alternate embodiment, the n-channel transistor can be replaced with p-channel transistors.
In another embodiment, an integrated circuit comprises a threshold voltage compensation circuit for providing a compensation voltage. The compensation circuit comprises a first n-channel transistor having a gate, drain and source fabricated in a first isolated p-type well, a current source coupled to the drain and the p-type well, and a voltage supply for coupling the gate to a reference supply. A second n-channel transistor is fabricated in a second isolated p-type well coupled to the first isolated p-type well for receiving the compensation voltage.
An integrated circuit memory device is described which comprises an array of memory cells, control circuitry for controlling operations of the memory device, a threshold voltage compensation circuit for providing a compensation voltage, and a transistor fabricated in an isolated well coupled to receive the compensation voltage. The compensation circuit comprises a first transistor having a gate, drain and source fabricated in a first isolated well, a current source coupled to the drain and the well, and a voltage supply for coupling the gate to a reference supply.
In yet another embodiment a method of compensating for threshold voltage variations in an integrated circuit device is described. The method comprises the steps of coupling a drain and isolation well of a first transistor to a current source, coupling a gate of the first transistor to a reference voltage such that the first transistor is activated and the well is biased to a compensation voltage, and coupling the compensation voltage to a well of a second transistor.
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De, V.K., et al., “Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI)”,1
Ahn Kie Y.
Forbes Leonard
Cunningham Terry D.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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