Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-22
2003-03-11
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S344000, C257S327000
Reexamination Certificate
active
06531736
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacture thereof, and more particularly to a semiconductor device including MISFETs (Metal-Insulator-Semiconductor Field Effect Transistors) and a method of manufacture thereof.
A conventional method of manufacturing MISFETs having metal gate electrodes will be described with reference to
FIGS. 1A
,
1
B, and
1
C.
First, as shown in
FIG. 1A
, a gate oxide layer
312
is formed on a p-type semiconductor substrate
311
. Next, a polysilicon layer
313
, a barrier metal layer
314
for suppressing the reaction of polysilicon and tungsten (W), and a metal layer
315
made of tungsten are deposited in sequence onto the gate oxide layer and then patterned using standard lithographic and RIE (Reactive Ion Etching) techniques to form gate electrodes. After that, p-type impurities are ion implanted into the substrate
311
using the gate electrodes as a mask to form source/drain diffusion layers
316
in the substrate.
Next, as shown in
FIG. 1B
, a silicon nitride layer
317
is deposited over the entire surface and then etched back by means of RIE techniques to leave a sidewall spacer of silicon nitride on the sidewall of the gate electrode.
Next, as shown in
FIG. 1C
, after the deposition of a silicon oxide layer
318
over the entire surface, the silicon oxide layer
318
is etched using a predetermined contact pattern to form contact holes
319
.
Note here that, in this example, the contact hole adjacent to the gate electrode is not formed using a self-aligned process.
Recently, semiconductor devices having a logic section and a memory section built into the same chip are in increasing demand.
In general, the logic section requires high-performance MISFETs as compared with the memory section. To achieve high performance, it is required to lower the sheet resistance of the diffusion layers of each MISFET. This is realized by forming a layer of silicide such as TiSi
2
or CoSi
2
.
In the memory section, the source/drain diffusion layers of the MISFETs are formed shallower than in the logic section. Thus, if a layer of silicide were formed on the diffusion layers of the MISFETs within the memory section, a spike would be produced at the bottom of the silicide layer. This would increase the possibility of being shorted to the substrate, resulting in an increase in junction leakage in the source/drain diffusion layers. It is therefore not desirable to form the layer of silicide in the MISFETs in the memory section.
However, according to conventional methods of manufacturing a semiconductor device having a logic section and a memory section built in, the addition of a process of forming a layer of silicide on the source/drain diffusion layers results in a problem that silicide is formed on the diffusion layers of both the MISFETs in the logic section and the MISFETs in the memory section and thus a structure in which no layer of silicide is existent in the memory section cannot be attained.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a semiconductor device which has, for example, a logic section and a memory section built into the same chip and permits the formation of such a structure that a layer of silicide is existent on the diffused regions of some MISFETs but nonexistent on the diffused regions of other MISFETs, thereby allowing the characteristics of the former MISFETs to be improved without degrading the characteristics of the latter MISFETs and a method of manufacture of such a semiconductor device.
The present invention also provides a semiconductor device having MISFETs which are low in gate resistance and small in gate-to-source/drain parasitic capacitance and a method of producing metal-gate MISFETs with good yield and high reliability.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a gate electrode formed on the gate insulating layer and including a lower electrode made of a first conductive layer and an upper electrode made of a second conductive layer lower in resistance than the first conductive layer; a first insulating layer selectively formed on a sidewall of the lower electrode of the gate electrode; a source/drain region including a diffused layer formed to self-align to the first insulating layer; and a layer of silicide formed on the source/drain region.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a gate electrode formed on the gate insulating layer; a. first insulating layer formed on a sidewall of the gate electrode; a second insulating layer formed on the first insulating layer; a source/drain region including a shallower diffused layer formed to self-align to the first insulating layer and a deeper diffused layer formed to self-align to the second insulating layer; and a layer of silicide formed on the source/drain region.
According to still another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a gate electrode formed on the gate insulating layer and including a lower electrode made of a first conductive layer and an upper electrode made of a second conductive layer lower in resistance than the first conductive layer; a first insulating layer selectively formed on a sidewall of the lower electrode of the gate electrode; a second insulating layer formed on a sidewall of the upper electrode and the first insulating layer covering the lower electrode of the gate electrode; a source/drain region including a shallower diffused layer formed to self-align to the first insulating layer and a deeper diffused layer formed to self-align to the second insulating layer; and a layer of silicide formed on the source/drain region.
According to still another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a gate electrode formed on the gate insulating layer and including a lower electrode made of a first conductive layer and an upper electrode made of a second conductive layer lower in resistance than the first conductive layer; a first insulating layer selectively formed on a sidewall of the lower electrode of the gate electrode; a second insulating layer formed on a sidewall of the upper electrode and the first insulating layer covering the lower electrode of the gate electrode; and first and second MISFETs formed in the semiconductor substrate and each having source/drain region, wherein the first MISFET has no silicide formed on its source/drain region and the second MISFET has silicide formed on its source/drain region.
According to still another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a gate electrode formed on the gate insulating layer; a first insulating layer formed on a sidewall of the gate electrode; a second insulating layer formed on the first insulating layer; and first, second and third MISFETs formed in the semiconductor substrate and each having source/drain region, wherein the first MISFET has no silicide formed on its source/drain region and the second and third MISFETs have silicide formed on their source/drain regions.
According to still another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a gate electrode formed on the gate insulating layer and including a lower electrode made of a first conductive layer and an upper electrode made of a second conductive layer lower in resistance than the first conductive laye
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Picardat Kevin M.
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