Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-24
2003-01-28
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S905000, C257S907000
Reexamination Certificate
active
06512276
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory such as a mask ROM (read only memory), and more specifically to a mask ROM having an improved cell layout which can minimize an influence of implanted code ions to an adjacent cell.
The mask ROM can be explained to be a ROM which was written with a predetermined content by utilizing a mask pattern in the course of an IC (integrated circuit) fabricating process.
In this mask ROM, a read-out data is generally handled as data having two values, namely, “0” and “1”. These two values are expressed as an on-bit and an off-bit in a flat cell type ROM. On the other hand, considering a threshold of a memory cell transistor, the on-bit and the off-bit are represented by a transistor having a low threshold and a transistor having a high threshold, respectively.
As a method for forming the low-threshold transistor and the high-threshold transistor, distinguishably from each other, the flat cell type ROM includes a method for selectively implanting boron, as an ion implantation impurity, in accordance with a content that is to be written in a mask ROM in the course of the IC fabricating process. This ion implantation is called a “code ion implantation” in the field of the ROM.
Japanese Patent Application Pre-examination Publication No. JP-A61-288464 discloses one example of a cell layout of the flat cell type ROM which was fabricated in accordance with the method capable of forming the low-threshold transistor and the high-threshold transistor, distinguishably from each other. Now, the prior art disclosed by JP-A61-288464 will be described with reference to
FIGS. 5
to
8
.
FIG. 5
is a diagrammatic plan view for illustrating the cell layout in accordance with the prior art, and
FIG. 6
is a diagrammatic sectional view taken along the line A—A in FIG.
5
.
As shown in
FIGS. 5 and 6
, in the prior art, a plurality of bit lines
1
, which become a source region and a drain region of memory cell transistors, are formed of N-type diffused regions
1
A which are formed in a principal surface of a semiconductor substrate
5
to extend in parallel to one another, separately from one another. A plurality of word lines
2
are formed on an insulating film
6
A formed on the principal surface of a semiconductor substrate
5
, to extend in parallel to one another, separately from one another, and orthogonally to the bit lines. This arrangement is a so-called flat cell.
In a flat cell ROM fabricating process, after a gate electrode constituting each word line
2
is formed, a P-type impurity is ion-implanted for a device isolation so that a P-type impurity diffused region (not shown in
FIG. 6
) is formed. Furthermore, an oxide film
6
is deposited to form an interlayer insulator film which covers the word lines
2
and the semiconductor substrate. Thereafter, a photolithography step is carried out for depositing a photoresist
4
for a ROM coding. Thus, the flat cell having the sectional structure shown in
FIG. 6
is obtained.
In this condition, code ion implanting openings
3
formed in the photoresist
4
are designed in the prior art to have the same width as a channel width of the memory cell transistor, as shown in FIG.
5
. However, since the code ion implantation is carried out after the interlayer insulator film
5
was formed, the energy required for the code ion implantation becomes high.
For example, in the case that a gate polycide constituting the word lines
2
is formed of a polysilicon of 0.1 &mgr;m thickness and a tungsten silicide of 0.15 &mgr;m thickness, and an interlayer film has a thickness of 0.3 &mgr;m to 0.4 &mgr;m, when boron is used a dopant, the code ion implantation requires an energy as high as 200 keV to 350 keV.
Therefore, if the code ion implantation is carried out using the cell layout disclosed by JP-A-61-288464 after the interlayer film was formed, since the ion implantation is carried with a high energy, a code ion implanted impurity diffused region
3
A (shown in
FIGS. 7 and 8
) becomes large in comparison with the case that, in a condition that the interlayer film has not yet been formed, the ion implantation is carried with an energy on the order of 100 kev to 150 keV. As a result, an effective channel width under an adjacent word line, namely, of an adjacent cell transistor, becomes narrow.
Now, the above mentioned influence will be described with reference to
FIG. 7
, which is a diagrammatic plan view for illustrating the spread of the impurity diffused region by the reference number
3
A when the ion implantation is carried with the high energy in the prior art cell layout.
In
FIG. 7
, a cell “C” to be noted is shown at the same position as that shown in FIG.
5
. This cell “C” to be noted is an on-bit cell, so that no boron ion is ion-implanted into the cell “C” to be noted, and on the other hand, the code ion implantation is carried out for eight cells adjacent to the on-bit cell “C” in eight directions. In the condition shown in
FIG. 7
, the influence of the adjacent cells to the on-bit cell “C” is the worst.
This would be seen from
FIG. 8
, which is a diagrammatic sectional view taken along the line B—B in FIG.
7
. As shown in
FIG. 8
, an effective channel width of the on-bit cell “C” is narrowed by the spread of the boron (the code ions) from an upper cell adjacent to the on-bit cell “C” and the spread of the boron (the code ions) from a lower cell adjacent to the on-bit cell “C”. As a result, the threshold of the on-bit cell “C” adversely becomes higher than a primarily expected threshold. This means that a reading margin of the cell in the mask ROM becomes small.
Here, it is considered to carry out the code ion implantation after the gate silicide (word line) is formed but before the interlayer film is formed, so that the code ion can be ion-implanted with a reduced energy. However, since it is strongly required to shorten a so-called TAT (turn around time) after a ROM coding data is given from a customer before a product is shipped to the customer, it is necessary to make the step of the code ion implantation as late as possible. Therefore, it is not practically acceptable to carry out the code ion implantation before the interlayer film is formed.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a semiconductor read only memory of the flat cell structure having a large reading margin by preventing the threshold of an on-bit cell (with no code ion implantation) from becoming high because of the influence of the spread of the code ions from adjacent cells.
According to the prevent invention, there is provided a semiconductor memory wherein bit lines are formed to have a predetermined angle to word lines.
According to the prevent invention, there is also provided a semiconductor memory wherein in a region where each bit line overlaps word lines, the bit line is perpendicular to the word lines, and in a region where each bit line does not overlap the word lines, the bit line has a predetermined angle to the word lines
According to the prevent invention, there is also provided a semiconductor memory comprising:
a plurality of bit lines formed by implanting a first impurity into a first predetermined region on a semiconductor substrate;
a first oxide film formed to cover the bit lines and the semiconductor substrate;
a plurality of word lines formed of a patterned polycide film composed of a polysilicon layer deposited on the first oxide film and doped with a second impurity and a silicide layer deposited on the polysilicon layer; and
a high-threshold transistor formed by implanting code ions into a second predetermined region on the semiconductor substrate,
wherein the bit lines are formed to have a predetermined angle to the word lines.
According to the prevent invention, there is also provided a semiconductor memory comprising:
a plurality of bit lines formed by implanti
McGinn & Gibb PLLC
NEC Corporation
Ngo Ngan V.
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