Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-08-15
2003-09-30
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189090, C365S226000
Reexamination Certificate
active
06628555
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a field of a memory device comprising semiconductor integrated circuits. Specifically, the present invention relates to a boosting power circuit required for driving the memory device.
BACKGROUND OF THE INVENTION
Regarding a dynamic memory device, as a method for having access to data of memory devices (memory cells) arranged in a matrix form, a potential is applied to word lines and data is exchanged between bit lines and the memory cells so as to perform reading and writing operations.
FIG. 12
shows memory cell arrays, a sense amplifier, and bit line precharge circuits of a typical dynamic random access memory (DRAM).
Reference numeral
111
denotes the memory cell arrays, reference numeral
112
denotes a bit line pair, reference numeral
113
denotes word lines, reference numeral
114
denotes bit line precharge circuits, reference numeral
115
denotes a sense amplifier, and reference numeral
116
denotes shared gates.
In the memory cell array
111
, as for a single memory cell capacitor Co, the memory cell capacitor Co is connected to the source of an access transistor TWL, the bit line
112
is connected to the drain of the access transistor TWL, and the word line
113
is connected to the gate of the access transistor TWL.
The DRAM stores data by accumulating electric charge in the memory cell capacitor Co. A DRAM operating source voltage has been reduced while the DRAM has higher density and larger capacity.
In order to sufficiently secure accumulated electric charge in the memory cell capacitor Co in response to lower source voltage, a method has been generally used for applying a source potential VDD to the memory cell capacitor Co at H level and applying a GND potential thereto at L level. Therefore, as a gate potential of the access transistor TWL for transferring accumulated electric charge to the memory cell capacitor Co, a boosted potential (VPP) is necessary, which is higher in potential than the DRAM source voltage. In order to obtain the potential, assuming that the DRAM source voltage is VDD and the transistor TWL has a threshold voltage of VT, VPPb=VDD+VT has to be satisfied.
Further, upon pre-charging the bit lines in response to lower source voltage VDD, in order to complete the pre-charging operation at high speed to increase a potential of the bit lines to a bit-line pre-charging potential VBP (=VDD/2), H level of a control signal of the bit line precharge circuit
114
is set at a boosted potential VPP.
Moreover, as shown in
FIG. 12
, the memory cell arrays (
111
(L),
111
(R)) on the both sides of the sense amplifier
115
share the sense amplifier
115
. This configuration has been generally adopted to reduce a layout area. Regarding the shared gates
116
as well used,for realizing the above configuration, a boosted potential VPP is set as H level of a gate voltage to accurately transfer data at high speed between the memory cell arrays
111
and the sense amplifier
115
.
As described above, in order to perform high-speed reading and writing operations in the DRAM in a stable manner, in addition to the source voltage VDD, a boosted power source VPP is necessary, which is set higher in potential than the source voltage. As a method for realizing such a voltage VPP, a boosting circuit having a charge pump circuit and so on therein is provided and the source voltage VDD is boosted to a high source potential VPP so as to obtain a high source potential.
FIG. 13
shows a conventional boosting power circuit.
Reference numeral
117
denotes a boosting circuit, reference numeral
118
denotes an auxiliary boosting circuit, reference numeral
119
denotes a timing control circuit, reference numeral
120
denotes an oscillator, reference numeral
121
denotes a detection circuit, and reference numeral
122
denotes an overboosting preventing circuit.
The boosting circuit
117
and the auxiliary boosting circuit
118
are realized by charge pump circuits which perform a boosting operation by transferring electric charge. Also, the outputs of the boosting circuit
117
and the auxiliary boosting circuit
118
are connected in parallel with each other.
The auxiliary boosting circuit
118
is provided for securing a boosted source potential VPP when a memory is in a standby status, which is achieved by setting its capability of supplying electric charge lower than that of the boosting circuit
117
so as to suppress consumption of current.
The boosting circuit
117
operates in synchronization with an internal memory activation signal IRAS when the memory is activated. Meanwhile, the auxiliary boosting circuit
118
operates asynchronously to the activation of the memory due to self-induced oscillation of the oscillator
120
, based on a result detected by the detection circuit
121
on a boosted source potential VPP.
The overboosting preventing circuit
122
is provided for preventing a temporary overboosting of a boosted voltage VPP particularly when a source voltage VDD is high. The overboosting preventing circuit
122
makes it possible to prevent damage on an element of the device and to obtain reliability.
Here,
FIG. 14
shows a schematic timing chart of the operation of the DRAM.
In
FIG. 14
, reference character CLK denotes a clock input signal, reference character RAS denotes a row address strobe input signal, reference character CAS denotes a column address strobe input signal, and reference character WE denotes a writing permission input signal.
In an example shown by
FIG. 14
, a reading cycle and a writing cycle are carried out in three clock periods. Pre-charging the bit lines is suspended substantially at the same time when the internal memory activation signal IRAS rises so as to determine a row address. And then, the word line corresponding to the selected row address is activated.
The word line is activated, so that electric charge accumulated in the memory cell capacitor is transferred to the bit line and a potential of the bit line is increased by a voltage value smaller than the bit line precharge potential VBP (=VDD/2) when H data is read. A potential of the bit line decreases by a voltage value smaller than the bit line precharge potential VBP when L data is read. In such a variation in potential of the bit line, a potential of the bit line is amplified to VDD at H level and to 0V at L level when the sense amplifier driving signal SE is set at H level.
The IRAS falls at a rising edge of the third clock, the word line is deactivated, and the sense amplifier driving signal SE is set at L level. Thereafter, a pre-charging operation for the bit line begins so as to precharge the bit line to the VBP. A series of operations are completed at this moment.
As indicated by circles in
FIG. 14
, the timings of consuming the boosted potential VPP generated in the boosting power circuit conform to the timing of activating the word line and the timing of operating a bit line precharge signal and the shared gates. This signal is substantially in synchronization with a rising edge and a falling edge of the internal memory activation signal IRAS.
In response to the above consumption of a boosted potential, as for the operation of the boosting circuit, it is possible to adopt two operating timings including performing a boosting operation only at a rising edge of the internal memory activation signal IRAS and performing a boosting operation at both of rising and falling edges of the IRAS.
As described above, as a timing of operating the boosting power circuit when the memory is in an activated status, it is possible to adopt two timings including operating in synchronization with a rising edge of the internal memory activation signal IRAS and operating both at rising and falling edges of the IRAS.
In a circuit using the former operating timing, boosted potentials conform to each other at a timing of activating the word lines. Meanwhile, electric charge is not supplied to the VPP by the boosting circuit upon precharging the bit line and activating the shared gates. Thus, a
Fujimoto Tomonori
Kondo Masataka
Oota Kiyoto
Sumimoto Yoshihiko
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
Phung Anh
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