Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-30
2003-04-08
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S392000, C257S410000
Reexamination Certificate
active
06545327
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) manufacturing method and device, and more particularly, a semiconductor IC device and manufacturing method for forming insulation layers by varying the carbon content therein.
DISCUSSION OF THE BACKGROUND
In a high-speed, high-functional conventional electronic circuit, highly independent and different functions, such as memory and logic, have been integrated on a large scale on different semiconductor substrates. Each of the semiconductor substrates is arranged on an insulated circuit board if required and is connected with metal interconnects. However, the lengths of metal interconnects formed on the insulated circuit board are much longer than the dimensions of an electronic element formed on the individual semiconductor substrates. Floating capacitance between surrounding insulating substances causes a large wiring delay. Therefore, such conventional technology is not suited for high-speed signal transmission between electronic elements on different semiconductor substrates. If the number of signal lines for a bus connecting different semiconductor substrates needs to be increased, the load capacitance of the bus increases; this increase in load capacitance degrades the noise resistance of the buffer circuit which drives the bus, causing erroneous operations to occur.
To resolve this problem and to provide a high-speed, and highly functional, electronic circuit, there is a growing demand for a monolithic IC which includes a plurality of electronic circuits formed on the same semiconductor substrate and having mutually fundamentally different functions. An example is an integrated system in a single-chip microcomputer and the like, comprising a central processor unit (CPU), which has a computing function, a memory, and a peripheral interface.
However, integrating a system on a single chip has some problems. For example, a metal-insulation-semiconductor field-effect transistor (MISFET), that constitutes a memory cell in a memory circuit, and a MISFET, that constitutes a logic circuit, have different threshold settings. Because of this difference in threshold settings, the different MISFETS are manufactured to have different gate-insulation layer thicknesses, substrate dopant concentrations, and the like during manufacturing steps. Differences in the functions of the MISFET used for the memory cell and the MISFET used for the logic circuit and the resulting different conditions are described in more detail below.
A memory cell, such as a dynamic random access memory (DRAM), comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), which has a silicon dioxide (SiO
2
) layer for the insulation layer, and also comprises capacitors, which are connected to the MOSFETs. The threshold voltage of a MOSFET cannot be set low because leakage current must be suppressed when the word line connected to the gate electrode of the MOSFET is turned off and electric charge stored in the capacitor must be retained. Especially when many uniform elements are integrated on the same substrate, the dopant concentration of the channel portion directly below a gate must be set high to suppress the short-channel effect which causes gate length dependency on threshold voltage. The gate length is the distance between source and drain electrodes.
In the memory cell, a voltage that is higher than the cell-array voltage (which is applied to the source electrode when the capacitor is charged) by at least the threshold voltage is applied to the word line. As described above, the threshold voltage for the MOSFET of the memory cell is also set high. Therefore, a large voltage is applied to the gate-oxide layer while the capacitor is being written. To prevent leakage current due to a high-voltage application or degradation of the gate-oxide layer, it is necessary that the electric field from the gate-oxide layer be kept small; that is, the gate-oxide layer must be made thick as described above. In an example of a conventional memory cell, the gate length is 0.35 &mgr;m, the cell-array voltage is 2.5V, the threshold voltage is 1.2V, and a voltage of 4.0V or larger is applied to the word line. To resist the electric field generated by the above, the gate-oxide layer must be approximately 10 nm thick.
In contrast to a memory cell, a MOSFET in logic circuit is not affected by leakage current, and it is desirable that the threshold voltage be set as low as possible to promote high-speed operation and sufficient driving capability.
Also, at certain levels, the short-channel effect does not affect the logic circuit performance, and it is desirable that the substrate dopant concentration in the channel portion be maintained as low as possible.
Further, the gate-oxide-layer thickness of the MOSFET in the logic circuit must be as thin as possible to obtain a sufficient driving capability. When the actual gate length is 0.35 &mgr;m for the logic circuit, as is standard, the commonly used threshold voltage is approximately 0.7V and the oxide-layer thickness is approximately 7 nm.
As described, to form MOSFETs with different threshold voltages, that is, with different channel concentrations and different gate oxide-layer thicknesses, a series of plural steps are performed to obtain each of the MOSFETs, thus increasing the manufacturing cost, which is disadvantageous. Even when oxide layers of the same thickness are made, if a part of them is thinned by an etching solution, such as an HF solution, a new pattern must be formed to protect the portion which needs to maintain the original oxide-layer thickness.
A technique introduced to resolve these problems replaces the logic MOSFET with the memory cell MOSFET so that the gate-oxide layers can have a single thickness. The threshold voltage for the memory cell decreases. As a result, a leakage current (negative voltage) tends to flow when the word line is off. This problem is avoided by applying a negative voltage to the word line when it is turned off, if the memory cell MOSFET has an n-type channel (T. Tsuruda et al.,
IEEE
1996, Custom Integrated Circuit Conference, No. 13.2).
However, in order to apply a negative voltage to the word lines whenever they are off, a voltage source circuit with large driving power is required, and the power must be supplied to fulfill the demand even during stand-by time. Even when the data are not exchanged, when the work line is off, the low-voltage circuit nonetheless still consumes some power. This situation is contradictory to the purpose of reducing power consumption. For example, a low-power electronic circuit is essential for portable compact information terminals and the like, but it is difficult to provide the low-power circuit with this method.
In addition, the gate-oxide layer of a MOSFET for the memory cell is made as thin as that of the MOSFET for the logic circuit. Unlike conventional technology, this arrangement makes it impossible to boost the word line over cell-array voltage by more than the threshold voltage. As a result, when the electric charges that can be stored in the memory cell decrease, frequent refreshing is needed, and power consumption increases, which is problematic.
Also, in a field-effect transistor (FET) using a polysilicon layer as a gate electrode to which boron atoms are added, boron penetration phenomena, in which boron atoms in the gate electrode penetrate to a channel region, (i.e., semiconductor substrate surface or SOI surface via the gate-insulation layer) is a problem. Penetration of boron atoms to the channel region changes the channel-dopant concentration, which determines the threshold voltage and the like; this phenomena makes it difficult to obtain device properties as desired or causes undesirable variation in properties among integrated devices.
In addition, to achieve a high-speed and highly functional, electronic circuit, in large-scale integration (LSI) specifically, there is a growing demand for miniaturization of FETs, which are a major constituent of L
Anderson Kill & Olick
Fahmy Wael
Lieberstein Eugene
Meller Michael N.
Pham Hoai
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