Method of forming a silicon oxide layer using pulsed...

Details Method of forming a silicon oxide layer using pulsed... Method of forming a silicon oxide layer using pulsed...

2001-10-22

2003-03-04

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S788000, C438S766000, C438S769000, C438S440000, C438S775000, C438S776000, C438S777000

Reexamination Certificate

active

06528434

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor devices and their manufacture, and more particularly, to a method of forming a silicon oxide layer with different thickness using pulsed nitrogen plasma implantation.
2. Description of the Prior Art
Metal-oxide-semiconductor (MOS) transistors usually function as an on/off switch device for a control signal. A MOS transistor comprises a gate electrode, a source/drain (S/D), and a silicon substrate. A gate oxide layer is thermally formed between the gate and the silicon substrate.
Circuits having different functions have been integrated on a single semiconductor wafer due to progress in design and technology, and now form what is called an embedded wafer. MOS transistors having different functions on the embedded wafer have different threshold voltages. This can be seen in a periphery I/O circuit with a core circuit of the logic integrated circuit having a different threshold voltage. The threshold voltage of the periphery I/O circuit is 3.3 volts, with the threshold voltage of the core circuit equal to 1.5 volts. The method of forming different thickness” of the gate oxide layer usually defines the threshold voltage value. The gate oxide layer is formed by performing a thermal oxidation process to oxidize the silicon substrate to form a silicon dioxide, with the thickness of the gate oxide layer thinner when the quality control is more difficult. Since the gate oxide layer properties influence the electrical properties of the MOS transistor as in the threshold voltage and the breakdown voltage, the key concern is the method to fabricate a gate oxide layer.
Please refer to
FIG. 1
to FIG.
3
.
FIG. 1
to
FIG. 3
are schematic diagrams of a fabrication of a silicon oxide layer
16
and
19
on a semiconductor substrate
10
. The semiconductor substrate
10
comprises a first region
22
and a second region
24
. An isolation trench
14
separates the first region
22
as shown in
FIG. 1. A
mask (e.g., a silicon nitride layer)
12
is formed on the surface of the semiconductor substrate
10
, with the mask
12
covering the first region
22
and exposing the second region
24
. A thermal oxidation process is then performed to form a silicon oxide layer
16
on the exposed second region
24
. An example of the thermal oxidation process is the Dry-Wet-Dry (DWD) process known in the art. Typically, the thermal oxidation process is performed in a temperature range from 900° C. to 1100° C. in a furnace for 6 hours to 8 hours. The mask
12
is subsequently removed.
As shown in
FIG. 3
, a second mask
18
is formed on the surface of the semiconductor substrate
10
to mask the second region
24
and to expose the first region
22
. A thermal oxidation process is performed in a furnace in order to form a silicon oxide layer
19
.
The gate oxide layer process in the prior art is formed using furnace oxidation technique known in the art. The process has a cycle time of 6 hours to 7 hours for completion of one batch. The lithography process is performed 2 or 3 times to form the different thickness of the gate oxide layer, with the different regions exposed by different photoresist layers. Finally the oxidation process is performed alone. Therefore, the different thickness of the gate oxide layer in the prior art is very slow and complicated thus affecting the throughput.
SUMMARY OF INVENTION
It is therefore the primary object of the present invention to provide a method for forming an oxide layer having a varying thickness in one cycle so as to increase throughput.
It is another object of the present invention to provide a method for a pulsed nitrogen plasma implantation of the silicon oxide layer.
In an embodiment of the present invention, a semiconductor substrate is firstly provided, which comprises a silicon surface with a first region and a second region. The method comprises firstly implanting a thin surface of the first region of the silicon surface by using a first predetermined concentration of Nitrogen ions. Then a thin surface of the second region of the silicon surface is implanted by using a second predetermined concentration of Nitrogen ions. An oxidation process is subsequently performed. The first predetermined thickness and the second predetermined thickness of the silicon oxide layer are formed simultaneously on the surface of the silicon in the first region and in the second region. Nitrogen ions are implanted in the surface of the silicon by forming the pulse nitrogen plasma in-situ. The first predetermined concentration is not equal to the second predetermined concentration.
It is an advantage of the present invention that the pulsed Nitrogen ion implantation process provides a thin distribution of the Nitrogen ions on the surface of the doped silicon, so the thickness of the gate oxide layer is limited in the subsequent thermal oxidation process. In addition, in other embodiments of the present invention, three or more different thickness of gate oxide layers are formed in one thermal oxidation process by using silicon surfaces doped with different dosages of Nitrogen ions cooperated with the undoped silicon surface.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 4764394 (1988-08-01), Conrad
patent: 5308787 (1994-05-01), Hong et al.
patent: 5882993 (1999-03-01), Gardner et al.
patent: 5918133 (1999-06-01), Gardner et al.
patent: 5942780 (1999-08-01), Barsan et al.
patent: 6165849 (2000-12-01), An et al.
H. R. Soleimani et al., Formation of Ultrathin Nitrided SiO2 Oxides by Direct Nitrogen Implatation into Silicon, J Electrochem Soc, vol. 142, No. 8, pp L132-I34.*
B. Doyle et al.., Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing, IEEE Electron Device Letters, vol. 16, No. 7, Jul. 1995.

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