Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-04-04
2003-04-15
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S150000, C438S151000, C438S162000
Reexamination Certificate
active
06548331
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a TFT used for liquid crystal display (LCD) and organic light emitting diode (OLED), etc. More particularly, the present invention relates to a TFT including a crystalline silicon active layer providing the source, drain, and channel regions of the TFT, and to a method for fabricating a TFT including the crystalline silicon active layer.
BACKGROUND OF THE INVENTION
Thin film transistor (TFTs) used for display devices such as liquid crystal display (LCD) and organic light emitting diode (OLED) is formed by depositing a silicon layer on a transparent substrate such as a glass or quartz, forming a gate and a gate electrode on the silicon layer, implanting dopant in the source and the drain regions of the silicon layer, performing an annealing to activate the dopant, and finally forming an insulation layer thereon. An active layer constituting the source, drain, and channel regions of a TFT is formed by depositing a silicon layer on a transparent substrate such as glass by means of chemical vapor deposition (CVD) and the like. The silicon layer directly deposited on the substrate by CVD is an amorphous silicon layer, which has low electron mobility. As display devices using thin film transistors requires high operation speed and miniaturized structure, the integration degree of its driving ICs becomes higher and the aperture ratio of the pixel region becomes lower. Therefore, it is required increase the electron mobility of the silicon layer in order to form the driving circuit concurrently with the pixel TFT and to enhance the pixel aperture ratio. For this purpose, technologies for forming a polycrystalline silicon layer having high electron mobility by crystallizing an amorphous silicon layer with thermal treatment have been in use as described below.
Solid phase crystallization (SPC) method is used to anneal an amorphous silicon layer at a temperature of 600° C. or below for a few hours or tens of hours. 600° C. is the temperature causing deformation of the glass constituting the substrate. However, the SPC method has the following disadvantages. Since the SPC method requires a thermal treatment for a long time, the SPC method has low productivity. In addition, when annealing a large-sized substrate, the SPC method causes deformation of the substrate during the extended thermal treatment even at a temperature of 600° C. or below.
Excimer laser crystallization (ELC) method locally generates a high temperature on the silicon layer for a very short time by scanning an excimer laser beam to instantaneously crystallize the silicon layer. However, the ELC method has the following disadvantages. The ELC method has difficulties in accurately controlling the scanning of the laser beam. In addition, since the ELC method processes only one substrate at a time, the ELC method has relatively low productivity as compared to a method wherein a plurality of substrates are processed in a furnace at one time.
To overcome the aforementioned disadvantages of the conventional silicon crystallization methods, a method of inducing crystallization of an amorphous silicon layer at a low temperature about 200° C. by contacting or implanting metals such as nickel, gold, and aluminum has been proposed. This phenomenon that low-temperature crystallization of amorphous silicon is induced with metal is conventionally called as metal induced crystallization (MIC). However, this metal induced crystallization (MIC) method also has following disadvantages. If a TFT is manufactured by the MIC method, the metal component used to induce the crystallization of silicon remains in the crystallized silicon providing the active layer of the TFT. The metal component remaining in the active layer causes current leakage in the channel region of the TFT.
Recently, a method of crystallizing a silicon layer by inducing crystallization of amorphous silicon in the lateral direction using a metal, which is conventionally refereed to as “metal induced lateral crystallization” (MILC), was proposed. (See S. W. Lee and S. K. Joo,
IEEE Electron Device Letter,
17(4), p. 160, 1996) In the metal induced lateral crystallization (MILC) phenomenon, metal does not directly cause the crystallization of the silicon, but the silicide generated by a chemical reaction between metal and silicon induces the crystallization of the silicon. As the crystallization proceeds, the silicide propagates in the lateral direction of the silicon inducing the sequential crystallization of the adjacent silicon region. As the metal causing this MILC, nickel and palladium or the like are known to those skilled in the art. Crystallizing a silicon layer by the MILC, a silicide containing crystallization inducing metal moves along the lateral direction as the crystallization of the silicon layer proceeds. Accordingly, little metal component is left in the silicon layer crystallized by the MILC. Therefore, the crystallized silicon layer does not adversely affect the current leakage or other characteristics of the TFT including the silicon layer. In addition, using the MILC, crystallization of silicon may be induced at a relatively low temperature of 300° C.~500° C. Thus, a plurality of substrates can be crystallized in a furnace at one time without causing any damages to the substrates.
FIG. 1A
to
FIG. 1D
are cross-sectional views illustrating a conventional method for crystallizing a silicon active layer of TFT using the MIC and the MILC methods. Referring to
FIG. 1A
, an amorphous silicon layer
11
is formed on an insulation substrate
10
having a buffer layer (not shown) thereon. The amorphous silicon layer
11
is patterned by photolithography so as to form an active layer. A gate insulation layer
12
and a gate electrode
13
are formed on the active layer
11
by using conventional methods. As shown in
FIG. 1B
, the substrate is doped with impurity using the gate electrode
13
as a mask. Thus, a source region
11
S, a channel region
11
C and a drain region
11
D are formed in the active layer. As shown in
FIG. 1C
, photoresist
14
is formed to cover the gate electrode
13
, the source region
11
S and the drain region
11
D in the vicinity of the gate electrode
13
, and a metal layer
15
is deposited over the substrate
10
and the photoresist
14
. As shown in
FIG. 1D
, after removing the photoresist
14
, the entire substrate is annealed at a temperature of 300-500° C. As a result, the source and drain regions
16
covered with the residual metal layer
14
are crystallized by the MIC caused by the metal layer
14
, and the metal-offset source and drain regions
15
not covered with the metal layer and a channel region
17
under the gate electrode
13
are respectively crystallized by the MILC propagating from the source and drain regions
16
covered with the metal layer
14
.
The photoresist
14
is formed to cover source and drain regions adjacent to the gate electrode
13
in order to prevent the current leakage in the channel region and the degradation of the operation characteristics of the same. If the metal layer
15
is formed to cover the entire source and drain regions, the current leakage and the degradation of the operation characteristics occur because the metal component used to cause the MIC remains in the channel region
11
C and the boundaries between the channel region and the source and the drain regions. Since the operation of the source and drain regions excluding the channel region are not substantially affected by the residual metal component, the source and drain regions apart from the channel region by a distance over 0.01~5&mgr;m is crystallized by the MIC caused by the MIC metal. Meanwhile, the channel region and the source and the drain regions adjacent to the channel region are crystallized by MILC induced by and propagating from the MIC metal. Crystallizing only the channel region and its vicinity by MILC, the time required to crystallize the entire active layer may be significantly reduced. However, when using the process shown in
FIGS. 1A
to
1
D, a step of
Joo Seung Ki
Lee Seok Woon
Baker & Botts L.L.P.
PT Plus Co. Ltd.
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