Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-07
2003-04-01
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S295000, C257S306000, C257S396000, C257S398000
Reexamination Certificate
active
06541807
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor and a method of manufacturing the same, and more specifically, it relates to a semiconductor device having a capacitor of a roughened surface shape and a method of manufacturing the same.
2. Description of the Prior Art
In recent years, the demand for semiconductor devices is rapidly expanded due to remarkable popularization of information devices such as computers. In function, a semiconductor device having a large storage capacity and capable of performing high-speed operations is required. Following this, technical development is progressed in relation to improvement in degree of integration and high-speed response or high reliability of the semiconductor device.
A DRAM (dynamic random access memory) is generally known as a semiconductor device capable of inputting/outputting stored information at random. This DRAM is formed by a memory cell array serving as a storage area storing a number of information and a peripheral circuit controlling memory cells included in the memory cell array for inputting/outputting the information from/to an external device.
The memory cell array occupies a large area on the semiconductor chip of such a DRAM. A plurality of memory cells for storing unit information are arranged on the memory cell array in the form of a matrix. Each memory cell is generally formed by a single MOS (metal oxide semiconductor) transistor and a single capacitor connected thereto, and widely known as a one transistor-one capacitor memory cell.
FIG. 23
is a schematic sectional view showing the structure of memory cells of a DRAM employed as a conventional semiconductor device having capacitors. Referring to
FIG. 23
, a plurality of MOS transistors
120
are formed on a surface of a silicon substrate
111
electrically isolated by a trench isolation
123
.
Each MOS transistor
120
includes a pair of source/drain regions
112
having an LDD (lightly doped drain) structure, a gate oxide film
113
and a gate electrode layer
114
. The gate electrode layer
114
has a polycrystalline silicon layer (hereinafter referred to as a doped polysilicon layer)
114
a
doped with an impurity and a tungsten silicide (WSi
2
) layer
114
b.
A silicon nitride film
115
is formed on the gate electrode layer
114
, and a silicon oxide film
116
is formed to cover the periphery thereof. A pad layer
117
a
and a bit line
117
b
are connected to the first and second ones of the pair of source/drain regions
112
respectively. An interlayer isolation layer
118
is formed on the overall surface of the silicon substrate
111
to cover the pad layer
117
a
, the bit line
117
b
and the MOS transistor
120
. A plug layer
119
is embedded in a hole
118
a
of the interlayer isolation layer
118
to come into contact with the pad layer
117
a
. A silicon nitride film
124
and a BPTEOS (borophosphotetraethyl orthosilicate) film
104
are formed on the interlayer isolation layer
118
. An opening
106
for each storage node
101
is formed in the silicon nitride film
124
and the BPTEOS film
104
.
Each capacitor
110
has the storage node
101
, a capacitor dielectric layer
102
and a cell plate
103
. The storage node
101
is formed along the side wall and the bottom wall of the opening
106
, and electrically connected to the source/drain regions
112
through the plug layer
119
and the pad layer
117
a
. The cell plate
103
is formed to be opposed to the storage node
101
through the capacitor dielectric layer
102
.
A method of manufacturing the conventional semiconductor device having capacitors is now described.
FIGS. 24
to
28
are schematic sectional views showing the method of manufacturing the conventional semiconductor device having capacitors in the step order. Referring to
FIG. 24
, the MOS transistor
120
, the pad layer
117
a
, the bit line
117
b
and the like are formed on the surface of the silicon substrate
111
formed with the trench isolation
123
. Thereafter the interlayer isolation layer
118
is formed to cover the surfaces thereof, and the plug layer
119
is formed to be electrically connected with the pad layer
117
a
. The silicon nitride film
124
and the BPTEOS film
104
are formed on the overall surface of the interlayer isolation layer
118
.
Referring to
FIG. 25
, the opening
106
for the storage node
101
is formed in the silicon nitride film
124
and the BPTEOS film
104
by general photolithography and etching.
Referring to
FIG. 26
, an amorphous silicon layer (hereinafter referred to as a doped amorphous silicon layer)
101
doped with an impurity is formed on the overall surface and thereafter subjected to surface roughening. Thus, the doped polysilicon layer
101
is formed with a roughened surface.
Referring to
FIG. 27
, photoresist
131
is embedded in the opening
106
. Anisotropic etching (etchback) is performed on the overall surface through the photoresist
131
defining a mask, until at least the upper surface of the BPTEOS
104
is exposed. Thereafter the photoresist
131
is removed.
Referring to
FIG. 28
, the doped polysilicon layer
101
is left along the side wall and the bottom wall of the opening
106
through the aforementioned etchback, to form the storage node
101
. Thereafter a natural oxide film is removed through buffer hydrofluoric acid (BHF) employing a mixed solution of hydrofluoric acid and ammonium fluoride.
Then, the capacitor dielectric layer
102
and the cell plate
103
are formed for manufacturing the semiconductor device having the capacitors
110
shown in FIG.
23
.
However, the conventional semiconductor device having capacitors is inferior in reliability. This problem is now described in detail.
(1) In the storage node
101
subjected to surface roughening as described above, crystal grains
101
b
of silicon grow on an underlayer
101
a
consisting of doped polysilicon, as shown in FIG.
29
. In this state, etching is performed with BHF in the conventional method for removing the natural oxide film. However, this BHF contains the mixed solution of hydrofluoric acid and ammonium fluoride, and this ammonium fluoride etches silicon.
Therefore, it is apprehended that the crystal grains
101
b
readily separate from the underlayer
101
a
in FIG.
29
and the separating crystal grains
101
b
adhere to the upper surface of the BPTEOS film
104
as shown in FIG.
30
. In this case, the storage node
101
may be shorted to the adjacent storage node
101
by the re-adhering crystal grains
101
b
, to reduce the reliability of the semiconductor device.
(2) In general, the etchback step shown in
FIGS. 27 and 28
is carried out through anisotropic etching. In this anisotropic etching, a residue is left along the side wall of the pattern due to the anisotropy of the etching. After the etchback step, therefore, the upper end of the storage node
101
defines a sharp forward end
101
c
along the side wall, as shown in FIG.
31
.
When etching is thereafter performed with BHF for removing the natural oxide film, the upper surface of the BPTEOS film
104
is removed and the forward end
101
c
projects beyond the upper end of the BPTEOS film
104
, as shown in
FIGS. 32 and 33
. The projecting forward end
101
c
is readily broken and separated due to vibration in a later washing step or the like. The separated forward end
101
c
may adhere to the upper surface of the BPTEOS film
104
. In this case, the storage node
101
is shorted to the adjacent storage node
101
to reduce the reliability of the semiconductor device, similarly to the aforementioned case (1).
(3) Aqueous hydrofluoric acid (HF+H
2
O) may be employed in place of BHF, in order to remove the natural oxide film. In this case, however, P (phosphorus) contained in the storage node
101
for providing conductivity is eluted from the surface of the storage node
101
into the aqueous hydrofluoric acid as phosphoric acid (PO
3
), as shown in FIG.
34
. Thus, the storage node
101
is reduced in conductivity, to
McDermott & Will & Emery
Meier Stephen D.
Mitsubishi Denki & Kabushiki Kaisha
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