Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-28
2003-09-16
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S365000, C257S366000, C438S157000
Reexamination Certificate
active
06621124
ABSTRACT:
The invention relates to a semiconductor device with a silicon semiconductor body having a first surface and a second surface facing away from the first, provided with a field effect transistor comprising a source, a drain, an interposed channel, and a first gate arranged opposite the channel on the first surface, said gate having a dimension along said first surface, and provided with a second gate provided on the second surface opposite the first gate.
The invention also relates to a method of manufacturing a semiconductor device with a silicon semiconductor body having a first surface and a second surface facing away from the first, and provided with a field effect transistor comprising a source, a drain, an interposed channel and a first gate provided on the first surface opposite the channel, and a second gate of a second gate material provided on the second surface opposite the channel.
Such a semiconductor device is known from JP-A-04 307972.
The known semiconductor device is provided with a second gate.
The use of a second gate is the suppression of short-channel effects in field effect transistors (FETs) with a comparatively short first gate. If the first gate is comparatively short, the channel between source and drain is comparatively short. Short-channel effects are effects in a field effect transistor having a short channel which are caused by the extension of the depletion region of the drain into the channel under the influence of a voltage on the drain. To suppress these short-channel effects, a second gate is present, and this second gate has to be accurately positioned opposite the channel of the FET. Field effect transistors are made increasingly smaller, with a shorter first gate and accordingly a shorter channel, especially for increasing the speed and the current-carrying power. There is a worldwide demand for improving the performance and reliability of FETs through the suppression of short-channel effects.
In the known semiconductor device, the second gate is manufactured by lithography and etching. It is practically impossible, however, to carry out lithographic operations on the second surface in locations which are accurately aligned with respect to the first surface.
As the gates of FETs are shorter, alignment errors and differences in dimensions of the second gate become relatively increasingly greater. In small FETs with gate lengths <100 nm, the operation is largely determined by the position and dimension of the second gate with respect to the first gate. If the second gate is not correctly aligned with respect to the first gate of the FET, there is an insufficient control over the channel, so that short-channel effects are insufficiently suppressed. If the second gate extends farther than only opposite the channel, moreover, there will be undesirable overlap capacitances between the second gate and the semiconductor body, whereby the speed of the transistor is seriously reduced. The spread in the properties of the products increases in proportion as the gate lengths are smaller.
A major disadvantage of the known device is that products from one and the same batch have diverging properties as a result of the method by which they were manufactured. The position of the second gate is not accurately defined with respect to the first gate of the FET and varies from one device to the next in devices belonging to one batch. Another disadvantage is that the dimension of the second gate also varies.
It is an object of the invention to provide a semiconductor device of the kind described in the opening paragraph in which the second gate has an accurately defined position with respect to the first gate.
The invention also has for its object to provide a method of manufacturing the device described in the opening paragraph which positions the second gate accurately with respect to the first gate.
This object is achieved in the device according to the invention in that the semiconductor body has a recess with a depth in the second surface, which recess is concentric with a substantially perpendicular projection of the first gate, and in which recess the second gate is present.
Since the semiconductor body has a recess in the second surface which is concentric with a substantially perpendicular projection of the first gate, the second gate being present in said recess, the second gate is closer to the channel in the semiconductor body than if no such recess were present in the semiconductor body. In addition, the distance from the second gate to the channel is shorter because the second gate lies substantially perpendicularly below the first gate, compared with the situation in which the second gate is laterally shifted.
There is a better control over the channel as a result, whereby short-channel effects are better suppressed. Lower source-drain series resistances are also realized, and the overlap capacitances between a portion of the second gate which may be present next to the channel and the semiconductor body are reduced. The performance of the FET is improved thereby. The current-carrying power and the speed are especially enhanced. The spread among products from one batch is also narrowed.
The dimension of the second gate may differ from that of the first gate, but in a favorable embodiment the second gate has a dimension along the second surface, averaged over the depth of the recess, which corresponds substantially to at most the dimension of the first gate.
Overlap capacitances between portions of the second gate laterally of a perpendicular projection of the first gate and the semiconductor body are substantially minimized. The speed of the transistor is improved thereby.
The location of the second gate is accordingly limited, and the dimension of the second gate is accordingly accurately defined with respect to the first gate of the FET, so that the properties of the semiconductor device are laid down within narrow limits.
The recess may be filled only partly, but it is favorable when the recess is completely filled by the second gate.
The material from which the second gate is made may be comparatively strongly doped polycrystalline silicon or a metal. A closed layer of gate material in the recess, for example a layer which covers the bottom wall of the recess, is sufficient already for a satisfactory operation of the second gate. To reduce the resistance of the second gate, it is favorable when the recess is completely filled with the second gate. It is alternatively possible, however, for the second gate to cover only a portion of the bottom wall and to be smaller than the first gate.
A gate dielectric may be present between the first gate and the first surface, so that the field effect transistor operates as a metal-insulator-semiconductor field effect transistor (MISFET). A field effect transistor with a gate dielectric has a lower gate leakage current than a field effect transistor without a gate dielectric.
A gate dielectric may be present in the recess, between the second gate and the semiconductor body, so that the second gate is capacitively coupled to the semiconductor body. A major advantage of a capacitive coupling is a low gate leakage current. The control of the second gate over the channel is better in proportion as the gate dielectric is thinner.
The semiconductor body lies on an oxide layer and, for example, a silicon substrate during the manufacture of the semiconductor device. It is favorable when the semiconductor body has a lowest possible parasitic capacitive coupling to the substrate. If a second substrate is present against the first gate and the first surface of the semiconductor body, the device will have an additional sturdiness for the purpose of removing the original silicon substrate and the oxide layer. If the second substrate has a dielectric constant which is lower than the effective dielectric constant of the oxide layer with the silicon substrate, the parasitic coupling between the semiconductor body and the second substrate will be reduced.
The object of the invention as regards the method is realized—acc
Booth Richard
Waxler Aaron
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