Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-03-20
2003-03-11
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C700S121000
Reexamination Certificate
active
06532182
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory production system, and a production method thereof, that infers the step in a wafer process that caused a defective semiconductor memory cell.
2. Description of the Related Art
In recent years, to improve the storage capacity of semiconductor memory, considerable effort has gone into the miniaturization of memory cells formed on chips.
If the development of a plurality of process steps (wafer process) necessary for the production of these miniaturized semiconductor memories and stabilization of these process steps are not performed rapidly, it is difficult to ship the required semiconductor memories at the time they are required.
Therefore, for the development and stabilization of each process step necessary for the production of semiconductor memory, it is essential to perform failure analysis of the semiconductor memory, and using the result obtained from this failure analysis repair the defect in the process step that caused the failure.
In general, judgment of whether the memory cells of a semiconductor memory are good or bad is performed such that predetermined data (“
0
”, “
1
”) is written to each memory cell bit by an LSI tester, then subsequently data is read out from this memory cell, and the two are compared to determine whether they match. The case where they match is designated as “pass bit”, the case of mismatch is designated as “fail bit”.
Various kinds of failure analysis are performed in respect of each individual semiconductor memory wherein the distribution condition of fail bits is generated and displayed in accordance with the arrangement of the memory cell array. This arrangement is called a fail bitmap, or just bitmap.
Japanese Examined Patent Application, Second Publication No. 6-18230 (hereunder referred to as First Prior Art) discloses a functional test performed automatically for all the chips in one wafer, and the test result is stored in a fail bit memory, and/or displayed on a screen and/or printed. At this time, for display in a limited area, the fail bit memory is divided into n×n blocks, and each block indicates the existence of a fail bit. Furthermore, when the contents of the fail bit memory are stored on an external storage device, to save memory capacity, one bit in one word (byte) corresponds to one bit of memory.
For example, with a 128 M bit semiconductor memory, the bitmap is 16 Mbytes for one chip. For one wafer (200 chips), 3.2 Gbytes of memory capacity is required, and for 1 lot (50 wafers), 160 Gbytes. Furthermore, if divided into 88 blocks, the memory capacity is 2.5 Gbytes per one lot, and the memory capacity can be reduced to {fraction (1/64)}th.
Japanese Unexamined Patent Application, First Publication No. 7-85697 (hereunder referred to as Second Prior Art) discloses a method of performing rapid failure analysis. In a memory map of a conventional semiconductor memory, fail bits with different failure modes, which have been caused by different failure causes, are mixed. As a result, the addresses are displayed as fail bits with different failure causes mixed in the abovementioned “fail bitmap”, which makes it difficult for a designer to identify the “failure mode” generated based on this “fail bitmap”, and further to infer the cause of the defect.
Here, “failure mode” means a unique fail bit distribution condition that appears in the case where a semiconductor memory having a specific failure, such as a defect etc., is tested in a predetermined condition, and it is known from experience that it shows different distribution conditions depending on the failure cause. For example, it includes a single bit failure in which there exists no fail bit before and after a target fail bit, a pair bit failure in which there exists a series of two fail bits, line failure (data line failure, or word line failure) in which there are more than three continuous bits and the like. Furthermore, the aforementioned “fail bitmap” is known as one of the devices suitable for identifying the distribution condition of fail bits.
Moreover, with the development of mass storage in recent semiconductor memory, this fail bitmap develops into a vast amount of data. Consequently, even if the First Prior Art is applied, it is difficult to output (print, display by CRT) the whole semiconductor memory as a fail bitmap at one time, which makes the operation of identifying the failure mode complicated. Furthermore, when analyzing the cause of the failure mode, the occurrence conditions must be analyzed for each individual fail bit. Therefore, there are also problems in that as the abovementioned “fail bitmap” becomes larger, the bitmap processing time in this analysis operation is greatly increased, and the analysis efficiency is reduced.
On the other hand, for a method to display the whole memory easily, a display method of a so-called “compressed bitmap” in that the fail bitmap is summarized is proposed in the First Prior Art. In this compressed bitmap, a plurality of bits in memory is converted into one unit of a compressed bit, and the object fail bitmap is compressed by a predetermined ratio. The display method using this compressed bitmap can display the distribution condition of the fail bits of the whole memory map concerned. However, the detail of the occurrence conditions cannot be detected (for example, it cannot be judged whether the digest bit displays one fail bit or a plurality of fail bits). Consequently, to analyze the cause of failure, one to one display of the “fail bitmap” is required, so that the failure mode analysis operation by a designer remains complicated.
To solve these problems, in the Second Prior Art, firstly a test is performed under predetermined measurement conditions. In the case where it is judged to be defecty, fail bit data are obtained. Here, in most cases the obtained fail bit data are fail bit data of compound failure modes in which a plurality of failure causes are intermixed. Therefore, an algorithm that detects a specific “failure mode” as a target is generated by a combination of address theory and the like, with which specific failure mode data are extracted, and fail bit data corresponding to the specific failure mode are obtained from the fail bit data initially obtained.
From the fail bit data in which various types of failure modes are intermixed, firstly pair bit failure mode is extracted, which is further classified into even number-odd number defect address pairs, or odd number-even number pairs. Then, if there is no pair bit defect, the defect is classified as a single bit failure address. If a series of defecty bits exists, it is classified as a line failure mode. By classifying in this manner, a failure corresponding to a specific failure mode can be extracted, hence it is easy to identify the occurrence conditions of the specific failure. Furthermore, the fail bitmap can be classified by failure mode for display at wafer scale.
With the Second Prior Art, the memory capacity can be small in comparison with the bitmap. However, the memory capacity changes greatly by failure mode. For example, with a 128 M bit semiconductor memory, 27 bytes are required to display one bit address. In a supposed case where one k byte of fail bits are scattered in one chip, 27 kbytes of memory capacity is required. For one wafer (260 chips) 675kbytes, and for one lot (50 wafers) 33 Mbytes of memory capacity is required. Furthermore, in the case where the fail bits are all pair defects, the memory capacity becomes half of this, so that 17 Mbytes of memory capacity is required.
Moreover, with the Second Prior Art, to extract the failure mode, a vast amount of time is required. For example, in the case where one k byte of fail bits exists, the algorithm that is shown in the drawing in the publication must be repeated thousands of times.
The following publication describes a method for estimating a defecty process step in a manufacturing process by utilizing defect information and the like that are detected by the above m
Hara Shin-ichi
Ogawa Sumio
Le Vu A.
NEC Corporation
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