Linear capacitor and process for making same

Details Linear capacitor and process for making same Linear capacitor and process for making same

2000-04-14

2003-04-08

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S532000

Reexamination Certificate

active

06545305

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field:
The present invention relates generally to semiconductor devices and in particular to a semiconductor capacitor. Still more particularly, the present invention relates to a linear capacitor and a process for fabricating the same.
2. Description of the Related Art:
Linear complementary metal oxide semiconductor (CMOS) products can benefit greatly from the availability of linear capacitors in which both terminals are isolated from the substrate and the voltage coefficient of capacitance in both directions are very small. Linear capacitors are useful for many applications, including filters, charge-redistribution networks, and compensation in standard two-stage amplifiers. The industry “workhorse” for linear capacitors in recent years has been the “poly-poly” or “polysilicon to polysilicon” capacitor. Integration of such capacitors has become increasingly difficult because the polysilicon doping is now often dictated by considerations in fabricating other devices.
In
FIGS. 1A-1C
, a known process for fabricating a linear capacitor is shown. In
FIG. 1A
, a substrate
100
with field oxide region
102
is formed thereon as shown. Substrate
100
is a semiconductor substrate, such as, silicon. Gate polysilicon layer
104
has been formed on exposed substrate
100
and field oxide region
102
. An N+ implant or diffusion is performed on this layer.
In
FIG. 1B
, an oxide layer
106
is formed that will create a poly-poly oxide layer for the linear capacitor. Thereafter, a second polysilicon layer is deposited, doped, and etched to form polysilicon top-plate
108
for the linear capacitor. The doping that forms polysilicon top-plate
108
is performed as part of a N+ source/drain implant. Doping of polysilicon top-plate
108
may be realized by diffusion, implantation, or doping as this layer is deposited.
Thereafter, in
FIG. 1C
, exposed portions of oxide layer
106
are stripped and polysilicon layer
104
is patterned and etched to form gate structure
110
and polysilicon bottom-plate
112
. Polysilicon bottom plate
112
forms the bottom portion of the linear capacitor.
In
FIGS. 2A-2C
, diagrams illustrating a known process for fabrication of a transistor and a linear capacitor are depicted. In
FIG. 2A
, substrate
200
is shown with field oxide region
202
. A polysilicon layer has been deposited, patterned, and etched to form polysilicon bottom-plate
204
.
Next, in
FIG. 2B
, gate oxidation is performed to form poly-poly oxide layer
206
for the linear capacitor. A second polysilicon layer is deposited, patterned, and then implanted with a N+ source/drain implant to form source/drain regions
208
and
210
. Then the second polysilicon layer is etched to form polysilicon top-plate
212
and gate structure
214
as illustrated in FIG.
2
C. The etching process also forms spacers
215
and
216
, which are artifacts of the etching process.
If the poly-poly oxide is not formed at the same time as the gate oxidation, another photocut is required to strip active regions for gate oxidation. Additionally, the doping in polysilicon top-plate
212
is doped in the same step as that for gate structure
214
. The amount of doping of the polysilicon layer forming polysilicon top gate is defined to optimize transistor and resistor performance, such as gate structure
214
. The resistance with the doping is typically 70 ohms to 150 ohms, which is not enough resistance for the capacitor. Low enough doping levels result in nonlinearities in capacitance. In other words, the capacitance changes when a direct current voltage is applied to the capacitor. Therefore, it would be advantageous to have an improved linear capacitor.


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