Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-11-24
2003-04-01
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S807000, C380S046000
Reexamination Certificate
active
06543022
ABSTRACT:
BACKGROUND
1. Field
The present invention relates to encoding of digital signals, and more particularly to encoding digital signals for transmission from one location to another.
2. Background Information
In a computer system, information may be stored and transferred in the form of digital binary signals known as bits. Bits may be transferred between hardware components, between software components and between hardware and software components in the computer system. Further, bits may be transferred from the computer system to another computer system by way of an external channel. The external channel may be embodied in numerous ways. For example, the external channel may comprise a coupling to a local area network, or to the Internet. The external channel may comprise a coupling to the public telephone network using a data modem, or a coupling to a cable television network using a cable modem. Alternatively, the external channel may comprise a coupling to a satellite system by way of a satellite transceiver. These are only some of the many possibilities for an external channel. When bits are transferred, they become vulnerable to accidental or intentional alteration during transmission but prior to reception at their destination.
An integrity check value (a binary digital signal comprising a sequence of bits) may be computed for bit sequences which are transferred (heretoafter referred to as “data bits”). The integrity check value may be used to determine whether the data bits have been altered during transmission. An integrity check value may be produced by an integrity check operation. The integrity check operation, when performed on differing data bit sequences, may produce different integrity check values. The integrity check operation may be performed by the sender of the data bits and transmitted to the receiver of the data bits. The receiver may then perform the same integrity operation on the data bits and compare it with the integrity check value transmitted by the sender. If the two integrity check values match, it is likely that the data bits were transmitted without alteration.
As digital signals are processed and transferred at ever increasing speeds, the need increases for an integrity check operation which makes available an integrity check value soon after the data bits are transmitted. A need exists for such an operation to be performed in hardware using simple circuits, or in software by way of the execution of instructions on a microprocessor. Furthermore, such an integrity check operation should be flexible enough to accommodate a variable number of data bits and produce an integrity check value with a variable number of bits.
SUMMARY
A circuit includes terminals to receive data bits and terminals to receive pseudo-random bits. The circuit further includes circuit elements each combining at least one data bit with at least one pseudo-random bit to produce an output signal on an output terminal. The circuit elements are configured into a plurality of rows, each row receiving at least one data bit of the plurality of data bits, at least one but less than all of the pseudo-random bits received by another row of circuit elements, and output signals of circuit elements of another row.
REFERENCES:
patent: 5361323 (1994-11-01), Murata et al.
patent: 5422919 (1995-06-01), Graham
patent: 5712863 (1998-01-01), Gray
patent: 5717535 (1998-02-01), French et al.
patent: 5745522 (1998-04-01), Heegard
patent: 6401226 (2002-06-01), Maeno
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tu Christine T.
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