Metal gate trim process by using self assembled monolayers

Details Metal gate trim process by using self assembled monolayers Metal gate trim process by using self assembled monolayers

2001-07-06

2003-04-08

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S624000, C438S672000, C438S694000, C438S700000

Reexamination Certificate

active

06544905

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices, and more particularly, to a trim process for a metal gate.
2. Discussion of the Related Art
The trend toward ultra large scale integration (ULSI) semiconductor technology, directed toward an effort to build integrated circuits with more and faster semiconductor devices, has resulted in continued shrinking of dimensions of the devices. For example, in circuits having field-effect transistors, a very important process is the formation of the gate for each transistor, in particular the width of such gate. In many applications, the switching speed and size of the transistor are functions of the width of the transistor gate. A narrower gate tends to produce a higher performance, i.e., faster transistor which is also smaller in size, i.e., narrower in width.
In a typical process for forming a metal gate device, photoresist
20
is patterned over a metal layer
22
disposed on an oxide layer
24
, in turn disposed on a silicon base
26
(FIG.
1
). The exposed metal is then etched, the patterned photoresist
20
being used as a mask during such etching step. Ideally, the formed gate is uniform in width, with such width being defined by and corresponding to the width of the photoresist mask
20
. However, as attempts are made to decrease the gate width to, for example, less than 40 nm, the etching process has proven difficult to control, such that the sides
28
,
30
of the gate
32
being formed become sloped and/or cupped in configuration, resulting in an improperly formed gate
32
(FIG.
2
).
Therefore, what is needed is a method for properly forming a metal gate of a transistor, which gate is a very small and configuration, i.e., less than 40 nm wide.
SUMMARY OF THE INVENTION
In the present method of forming a metal gate of a semiconductor device, a substrate is provided, which substrate includes a substrate body and a dielectric layer thereon. A metal layer is provided over the dielectric layer, and a layer of photoresist is provided over the metal layer. The photoresist is patterned to expose portions of the metal layer, and the metal layer is etched, using the patterned photoresist as a mask. During such etching process, portions of the metal layer are etched away to in turn expose portions of the dielectric layer and leave a metal body on the dielectric layer, the metal body having a top surface and side surfaces. A self assembled monolayer is provided over the exposed portions of the dielectric layer and the top surface and side surfaces of the metal body, having ordered regions covering the top surface of the metal body and covering the exposed portions of the dielectric layer and disordered regions covering the side surfaces of the metal body. The resulting structure is etched, the disordered regions of the self assembled monolayer allowing etching of the side surfaces of the metal body while the ordered regions of the self assembled monolayer substantially block etching of the top surface of the metal body and exposed portions of the dielectric layer.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described (an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.


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Joanna Aizenberg, Andrew J. Black, George M. Whitesides, Controlling Local Disorder in Self-Assembled Monolayers by Patterning the Topography of Their Metallic Supports, Nature, vol. 394, Aug. 27, 1998, pp. 868-870.

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