Methods of forming transistors and connections thereto

Details Methods of forming transistors and connections thereto Methods of forming transistors and connections thereto

2000-12-11

2003-01-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S151000, C438S155000, C438S161000, C438S253000, C438S396000

Reexamination Certificate

active

06509213

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and related integrated circuitry.
BACKGROUND OF THE INVENTION
Semiconductor device fabrication typically involves fabrication of transistors relative to a substrate. One type of transistor is a MOS transistor which includes a conductive gate and diffusion regions which serve as the source and drain of the transistor. Individual transistors are often separated from one another by isolation regions which serve to electrically insulate transistor components from one another. One type of substrate upon which such transistors can be formed is a silicon-on-insulator (SOI) substrate which comprises individual islands of semiconductive material formed atop and surrounded by insulator material, which is typically an oxide material. Transistors are formed over or within semiconductive islands, with insulator material separating the islands. Another type of substrate upon which such transistors can be formed is a bulk semiconductive substrate such as monocrystalline silicon. Such substrates typically comprise active areas within which desired transistors are formed, with such areas being separated by oxide isolation regions.
Typically, electrical interconnections between transistors or other devices are formed by providing an insulating layer of material over the substrate and an associated transistor location with which electrical connection is desired, and then etching a contact opening through the insulating material to the transistor location. Subsequently, conductive material is deposited within the contact opening and electrically connects with the desired transistor location. Forming an interconnection in this manner requires at least one additional layer of material (the BPSG material) and additional processing steps which prolong the fabrication process.
One type of integrated circuitry in which the above electrical interconnections can be made is dynamic random access memory (DRAM) circuitry. DRAM cells utilize storage capacitors which are operably associated with MOS transistors. Storage capacitors are typically formed, within and relative to insulating material which is formed over the substrate. The amount of charge a particular capacitor can store is proportional to the amount of capacitor storage node surface area. As DRAM dimensions grow smaller, there is a push to maintain storage capacitance values despite denser circuitry.
This invention grew out of concerns associated with improving the manner in which wafer space is utilized to support integrated circuitry constructions. This invention also grew out of concerns associated with improving the manner in which integrated circuitry electrical interconnections are formed.
SUMMARY OF THE INVENTION
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate. Conductive material is formed which is received within at least one of the isolation regions.
In one preferred implementation, a silicon-on-insulator (SOI) substrate is utilized to support integrated circuitry which is formed utilizing the methodical aspects of the invention. In another preferred implementation, other substrates, such as conventional bulk substrates are utilized.


REFERENCES:
patent: 4604162 (1986-08-01), Sobczak
patent: 4700461 (1987-10-01), Choi et al.
patent: 5011783 (1991-04-01), Ogawa et al.
patent: 5214603 (1993-05-01), Dhong et al.
patent: 5391911 (1995-02-01), Beyer et al.
patent: 5539229 (1996-07-01), Noble, Jr. et al.
patent: 5599724 (1997-02-01), Yoshida
patent: 5608248 (1997-03-01), Ohno
patent: 5763931 (1998-06-01), Sugiyama
patent: 5831305 (1998-11-01), Kim
patent: 5846854 (1998-12-01), Giraud et al.
patent: 6004835 (1999-12-01), Noble
patent: 6004865 (1999-12-01), Horiuchi et al.
patent: 6091129 (2000-07-01), Cleeves
patent: 6117760 (2000-09-01), Gardner et al.
patent: 6225147 (2001-05-01), Noble
patent: 6274919 (2001-08-01), Wada
patent: 6373138 (2002-04-01), Noble
patent: 0 720 221 (1996-07-01), None
Kuge et al.,SOI-DRAM Circuit Technologies For Low Power High Speed Multigiga Scale Memories, IEEE Journal of Solid State Circuits,Apr. 1996, pp. 586-591.
Suma et al.,An SOI-DRAM With Wide Operating Voltage Range by CMOS/SIMOX Technology, IEEE Journal of Solid State Circuits,Nov. 1994, pp. 1323-1329.
Bakeman et al.,A High Performance 16-Mb DRAM Technology, 1990 Symposium on VLSI Technology Digest of Technical Papers,Honolulu, HI, Jun. 4-7, pp. 11-12.
Kohyama et al.,Buried Bit Line Cell for 64MB DRAMs, IEEE 1990 Symposium on VLSI Technology,pp. 17-18.
Davari et al.,A Variable-Size Shallow Trench Isolation (STI) TechnologyWith Diffused Sidewall Doping for Submicron CMOS, IEDM Technical Digest, International Electron Devices Meeting,San Francisco, CA, Dec. 11-14, 1988, pp. 92-95.
Buried Stud that Eliminates Substrate and Well Contact Requirements,IBM Web page, Jun. 1996, 2 pgs.
Takahiro Onai et al., “SEPIA: A New Isolation Structure for Soft-Error-Immune LSI's,” 1993 IEEE 3 pages.

Affiliated with

Also associated with

Rating

Methods of forming transistors and connections thereto does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of forming transistors and connections thereto, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming transistors and connections thereto will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3065641