Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2002-06-24
2003-04-15
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S786000, C257S207000, C324S763010
Reexamination Certificate
active
06548910
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an integrated circuit chip in which a plurality of circuit modules are integrated, an integrated circuit element with the integrated circuit chip packaged therein, and an electronic device with the integrated circuit element mounted therein.
Recently, in the integrated circuit field, a design rule for fabrication of a semiconductor has become finer and a circuit scale which can be integrated per unit area increases as the techniques for semiconductor fabrication progresses. Therefore, the size of an integrated circuit chip can be reduced as compared with before, if the circuit scale is the same. On the other hand, a width of a data bus of a digital signal processing circuit in the integrated circuit has increased as compared with before. Due to the synergy of the increase of the integration density and enlargement of the data bus width, the number of the input/output (I/O) terminals necessary for inputting/outputting a signal between the integrated circuit in the chip and external equipment increases more and more. Conventionally, the I/O terminals are arranged in a row along edges of the chip. For example, when the chip is square, the terminals are arranged on four sides of the square without leaving a gap between each of the terminals. The I/O terminals each usually have a bonding pad and a buffer circuit. The buffer circuit functions to protect circuit modules in the chip from external noises and it ordinarily comprises a transistor having a relatively large capacitance.
The integrated circuit chip is mounted on the printed circuit board of an electronic device by either of two methods.
One method is such that the integrated circuit chip is encapsulated in a package of a resin to form an integrated circuit element and the integrated circuit element is mounted on a printed circuit board. In this case, bonding pads of the I/O terminals in the chip are connected to terminals of the package for external connection by wire bonding and the connected portions are sealed in the package. When the terminals for external connection are connected to the printed circuit board, the integrated circuit chip and the printed circuit board are connected each other. According to this method, the circuit modules on the chip are protected by the package, which enhances reliability.
Another method is a so-called direct bonding method where a chip is directly bonded on a printed circuit board. Since the chip is directly wire-bonded on the printed circuit board in the form a of so-called bare chip, without being encapsulated in a package, a space needed for arranging the integrated circuit chip on the printed circuit board is reduced by a space corresponding to that which a package would have taken. In addition, advantageously, the cost of the package can also be saved.
As mentioned above, although the circuit modules in the chip are reduced in size as the semiconductor fabrication process becomes finer, a pitch of the I/O terminals does not reduce as much. This is so because there is a limit to the amount by which an interval between wires or between a wire and an adjacent lead during wire bonding may be reduced while still avoiding an electrical short circuit between wires adjacent to each other or an electrical short circuit between a wire and an adjacent lead.
Thus, even if the chip size is determined from the view point of the scale of the circuit modules in the chip, a peripheral length of the chip is not large enough for arranging the I/O terminals along the length. For this reason, the chip size should be determined based on the number of the I/O terminals (a phenomenon known as “pad neck” which occurs when it is not possible to further reduce a chip size due to the number of I/O terminals). In a “pad necked” chip, the chip size is larger than necessary for the scale of the circuit modules in the chip and, therefore, a vacant area where no circuit modules are disposed is present. The vacant area is located in an inner area of the chip, while the I/O terminals are disposed around the periphery of the chip without a gap between each of the terminals.
If the chip size is larger than necessary for the circuit modules, the chip cost is correspondingly high.
The present invention is made in view of the facts as mentioned above, and it is an object of the present invention to provide an integrated circuit chip which is capable of avoiding pad necking and has an optimum size for its circuit scale.
SUMMARY OF THE INVENTION
According to the invention, there is provided an integrated circuit chip comprising a substrate, circuit modules formed on the substrate, and input/output terminals for inputting/outputting a signal to/from the circuit modules; the input/output terminals including input/output terminals for operation time which input/output a signal during operation of the circuit modules and input/output terminals for inspection which inspect the circuit modules; and the input/output terminals for operation time being arranged on the substrate along edges of the substrate and the input/output terminals for inspection and the circuit modules being arranged on the substrate in an inner area than the input/output terminals for operation time.
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Jr. Carl Whitehead
Lerner David Littenberg Krumholz & Mentlik LLP
Sony Computer Entertainment Inc.
Vesperman William
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