Integrated circuits having plugs in conductive layers...

Details Integrated circuits having plugs in conductive layers... Integrated circuits having plugs in conductive layers...

1999-09-02

2003-04-08

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000, C257S760000, C257S763000, C257S774000, C438S629000, C438S672000, C438S675000

Reexamination Certificate

active

06545358

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 98-38200, filed Sep. 16, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF INVENTION
The present invention relates to integrated circuits in general, and more particularly, to multi-layer wiring in integrated circuits.
BACKGROUND OF THE INVENTION
As the level of integration increases, the complexity and density of devices and structures in integrated circuits may also increase. As a result, multi-layered metal wiring may be used to achieve desired densities. It is known, for example, to form via holes filled with conductive material (or plugs) between different metal wiring layers in the integrated circuit to provide the desired interconnections between layers.
FIG. 1
is an enlarged cross-sectional view of a conventional multi-layer wiring structure in an integrated circuit. Referring to
FIG. 1
, a lower metal layer
3
is formed on a substrate
1
. A capping layer
5
and an interlayer insulating layer
7
having a via hole
8
that exposes the lower metal layer
3
are formed on the lower metal layer
3
. A plug
9
is formed in the via hole
8
and is connected to the lower metal layer
3
. An upper metal layer
11
is formed on the plug
9
and the interlayer insulating layer
7
. The lower metal layer
3
is electrically coupled to the upper metal layer
11
through the plug
9
.
As the density of integrated circuit increases, however, spacing between via holes may be reduced and the contact surface area between the plug
9
and the upper and lower metal layers
11
and
3
may be reduced, which may increase the contact resistance therebetween.
Also, according to some conventional methods of forming multi-layered metal wiring, the plug
9
may be formed by depositing a plug metal layer and planarizing the plug metal layer using Chemical Mechanical Polishing (CMP) or an etch-back process. Unfortunately, the CMP or etch back process may cause the plug
9
to be separated from the via hole
8
or to be detached from the lower metal layer
3
. Accordingly, there is a need for improved multi-layer wiring between metal layers in integrated circuits and related methods.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to allow improved multi-layer wiring structures in integrated circuits and related methods.
It is another object of the present invention to allow multi-layer wiring structures in integrated circuit structures that may provide reduced electrical resistance.
These and other objects of the present invention can be provided by integrated circuit structures that include a first conductive layer on a substrate, wherein the first conductive layer has a recess in a surface thereof, opposite the substrate and that include a first plug in the recess. An insulating layer on the first conductive layer and on the first plug has a hole therein that exposes a portion of the first plug. A second plug is in the hole and a second conductive layer is on the insulating layer and on the second plug in the hole. Accordingly, a contact area between the first plug and the lower metal layer can be increased, thus reducing a contact resistance therebetween.
In a further aspect of the present invention, the first plug can include a first plug surface in the recess in the first conductive layer and the second plug can include a second plug surface on the exposed portion of the first plug, wherein the first plug surface is larger than the second plug surface. In other words, the first plug can have a cross-sectional size greater than a cross-sectional size of the second plug, thus allowing a reduction in the resistance between the first and second conductive layers. In another aspect of the present invention, a cross-sectional size of the recess can be greater than a cross-sectional size of the hole. Since the first plug is formed in the recess having a larger cross-sectional size, the likelihood that the first plug will become detached from the recess or separated from the interface with the lower metal layer can be reduced.
In yet another aspect of the present invention, the first plug extends from the recess onto a surface of the first conductive layer adjacent the hole and opposite the substrate.
Structures and methods according to the present invention can thus provide reduced resistance between conductive layers in multi-layer wiring structures.


REFERENCES:
patent: 4933743 (1990-06-01), Thomas et al.
patent: 5595936 (1997-01-01), Choi et al.
patent: 5619071 (1997-04-01), Myers et al.
patent: 5635763 (1997-06-01), Inoue et al.
patent: 5710462 (1998-01-01), Mizushima
patent: 5739049 (1998-04-01), Park et al.
patent: 5767010 (1998-06-01), Mis et al.
patent: 5932907 (1999-08-01), Grill et al.
patent: 5939788 (1999-08-01), McTeer
patent: 6008114 (1999-12-01), Li
patent: 6150206 (2000-11-01), Oh
patent: 6194309 (2001-02-01), Jin
patent: 8-274172 (1996-10-01), None
patent: 11054617 (1999-02-01), None
patent: 11330399 (1999-11-01), None
Notice to Submit Response, Korean Application No. 98-38200, Jun. 23, 2000.

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