Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-19
2003-04-29
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S628000, C438S637000, C438S669000, C438S685000, C438S688000, C438S785000, C438S786000
Reexamination Certificate
active
06555465
ABSTRACT:
This application is based on Japanese patent application HEI 9-352434 filed on Dec. 5, 1997, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a multi-layer wiring structure of integrated circuit suitable for LSI and the like and a method of forming a multi-layer wiring.
b) Description of the Related Art
Conventionally, a multi-layer wiring structure such as shown in
FIG. 23
is known.
On the surface of a semiconductor substrate
1
made of silicon or the like, an insulating film
2
made of silicon oxide or the like is formed. A contact hole
2
a
is formed through the insulating film
2
in the area corresponding to a connection area
1
a
(e.g., impurity doped region) in the surface layer of the substrate. A first wiring layer
3
is formed on the insulating film and connected via the contact hole
2
a
to the connection area
1
a
of the substrate surface.
On the insulating film
2
, an interlayer insulating film made of phosphosilicate glass (PSG) or the like is formed covering the wiring layer
3
. A contact hole
4
a
is formed through the insulating film
4
in an area corresponding to a partial area of the wiring layer
3
. On the insulating film
4
, a second wiring layer
5
is formed, while being connected via the contact hole
4
a
to the wiring layer
3
.
As an example of the wiring layer
3
, a lamination structure is known (e.g., refer to U.S. Pat. No. 5,070,036). This lamination structure is made of, as shown in
FIG. 24
, a Ti layer
3
a
of 2 to 10 nm in thickness, a TiN or TiO
x
N
y
(x=0.05 to 0.2, y=0.95 to 0.8) layer
3
b
of 50 to 200 nm in thickness, a Ti layer
3
c
of 7 to 20 nm in thickness, an Al alloy (Al—Si—Ti, or the like) layer
3
d
of 300 to 1000 nm in thickness, a Ti layer
3
e
of 7 to 20 nm in thickness, and a TiO
x
N
y
(x=0.1 to 0.3, y=0.9 to 0.7) layer
3
f
of 50 to 500 nm in thickness, respectively stacked in this order from the bottom.
As another example of the wiring layer
3
, a lamination structure is known (e.g., refer to JP-A-HEI-5-190551). This lamination structure is made of, as shown in
FIG. 26
, a TiN layer
3
A, an Al alloy (or Al) layer
3
B, a Ti layer
3
C, and a TiN layer
3
D, respectively stacked in this order from the bottom.
According to the conventional technique shown in
FIG. 24
, while the TiON layer
3
f
is formed on the Ti layer
3
e
through sputtering, the surface of the Ti layer
3
e
is oxidized and a TiO
x
film
3
g
having a high resistivity is formed as shown in FIG.
25
. Since this layer having a high resistivity is interposed between the Ti layer
3
e
and TiON layer
3
f
, the resistance (via resistance) of the interlayer contact area between the wiring layers
3
and
5
increases by about 20%.
According to the conventional technique shown in
FIG. 26
, since the TiN layer
3
D is formed on the Ti layer
3
C, the surface of the Ti layer
3
C is free from oxidation. However, according to the studies made by the inventor, it has been found that the resistance (via resistance) of the interlayer contact area increases if a plug embedded type wiring layer is formed as the wiring layer
5
.
FIG. 27
shows an example of a conventional multi-layer wiring structure. Like elements to those shown in
FIGS. 23 and 26
are represented by using identical reference numerals and the detailed description thereof is omitted. On an insulating film
2
, a lamination structure is formed which is made of a Ti layer
3
E of 10 to 20 nm in thickness, a TiN layer
3
A of 100 nm in thickness, an Al alloy (Al—Si—Cu) layer
3
B of 350 nm in thickness, a Ti layer
3
C of 10 nm in thickness, and a TiN layer
3
D of 50 nm in thickness, sequentially stacked in this order from the bottom. A lamination of the Ti layer
3
E/TiN layer
3
A under the Al alloy layer
3
B constitutes a tight adhesion layer for the Al alloy layer
3
B, and a lamination of the TiN layer
3
D/Ti layer
3
C functions as a protective layer for the Al alloy layer
3
B. The lamination wiring structure is patterned in a desired wiring pattern to form a wiring layer
3
.
On the insulating film
2
, an insulating film
4
is formed covering the wiring layer
3
. A contact hole
4
a
is formed through the insulating film
4
by selective dry etching. During this selective dry etching, pin holes P may be formed through the lamination of the Ti layer
3
C /TiN layer
3
D. Next, a tight adhesion layer
6
is formed covering the inner surface of the contact hole
4
a
and the upper surface of the insulating film
4
. As the tight adhesion layer
6
, a lamination of a Ti layer and a TiN layer stacked upon the Ti layer is used. The coverage of the tight adhesion layer
6
lowers at the areas where the pin holes P are formed.
Next, a W layer is formed over the substrate through blanket chemical vapor deposition (CVD). Thereafter, the W layer is etched back to leave a plug
7
made of W in the contact hole
4
a
. Blanket CVD generally uses WF
6
as a source gas. Therefore, WF
6
reaches the Al alloy layer
3
B via the coverage lowered areas of the pin holes P and forms a high resistance aluminum fluoride (AlF
x
) layer
8
by the following chemical formula.
WF
6
+Al→AlF
x
+W
Thereafter, a wiring material layer made of Al alloy or the like is formed over the substrate. By pattering the lamination of the wiring material layer and tight adhesion layer
6
, a second wiring layer connected to the plug
7
is formed. Since the high resistance AlF
x
layer
8
exists at the interlayer contact area between the second wiring layer and the wiring layer
3
, the via resistance increases. An increase of the via resistance changes with the conditions of the generated AlF
x
layer
8
, and the via resistance distributes in a range from a two- to threefold to a tenfold of a standard via resistance or further larger.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a novel multi-layer wiring structure or wiring layer forming method capable of suppressing a resistance increase in the interlayer contact area.
According to one aspect of the present invention, a multilayer wiring forming method comprises the steps of:
forming an Al or Al alloy layer on a first insulating film covering a substrate;
forming a first Ti layer on the Al or Al alloy layer;
sequentially laminating a first TiN layer and a first TiON layer in this order on the first Ti layer through reactive sputtering;
patterning a lamination of the Al or Al alloy layer, the first Ti layer, the first TiN layer, and the first TiON layer into a desired wiring pattern to form a first wiring layer;
forming a second insulating film on the first insulating film, the second insulating film covering the first wiring layer;
forming a contact hole through the second insulating film, the contact hole reaching a partial surface area of the first TiON layer;
forming a tight adhesion layer covering an inner surface of the contact hole;
forming a conductive plug embedding an inside of the contact hole, with the tight adhesion layer being interposed under the conductive plug; and
forming a second wiring layer on the second insulating film, the second wiring layer being connected to the plug.
With the resulting structure, the first wiring layer is a lamination of the Al or Al alloy layer, first Ti layer, first TiN layer, and first TiON layer. The Al or Al alloy layer is a main wiring layer of the first wiring layer. The first Ti layer prevents the surface of the Al or Al alloy layer from being nitrided while the first TiN layer is formed. The first TiN layer prevents the surface of the first Ti layer from being oxidized while the first TiON layer is formed. The first TiON layer functions as an antireflection layer during a photolithography process for patterning the first wiring layer and also prevents generation of pin holes during a dry etching process for forming the contact hole in the second insulating film.
A nitride film is therefore hard to be formed on the surface
Dickstein , Shapiro, Morin & Oshinsky, LLP
Fourson George
Garcia Joannie Adelle
Yamaha Corp.
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