Reduction of damage in semiconductor container capacitors

Details Reduction of damage in semiconductor container capacitors Reduction of damage in semiconductor container capacitors

2000-12-20

2003-03-25

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S306000

Reexamination Certificate

active

06538274

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to development of semiconductor container structures, and in particular to the development of semiconductor container capacitor structures in conjunction with a diffusion barrier layer overlying a surrounding insulating layer and to apparatus making use of such container capacitor structures.
BACKGROUND OF THE INVENTION
Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor includes two conductive plates. The top plate of each capacitor is typically shared, or common, with each of the other capacitors. The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as bit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line.
The memory cells are typically arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to an address decoder. In response to the decoded address, row access circuitry activates a word line. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. In response to the decoded column address, column access circuitry selects a bit line. For a read operation, the selected word line activates the access transistors for a given word line address, and data is latched to the selected bit line.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing memory cell size and its accompanying capacitor surface area, since capacitance is a function of surface area. Additionally, there is a continuing goal to further decrease memory cell size.
A principal approach to increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. One common form of stacked capacitor structure is a cylindrical container stacked capacitor, with a container structure forming the bottom plate of the capacitor. Another method of increasing cell capacitance is through the use of high surface-area materials such as hemispherical-grain polysilicon (HSG) which increase available surface area for a given foot print due to their roughened or irregular surfaces. Additional approaches to increasing cell capacitance may include reducing the thickness of the dielectric layer of the cell capacitor.
As cell size decreases, container structures must be formed in closer proximity to neighboring container structures. At close proximity, care must be taken to avoid shorting the bottom plates of adjacent cell capacitors. Capacitors having such shorted container structures will result in defective memory cells, as the cells will be unable to accurately store data.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative semiconductor container capacitor structures and methods of producing same.
SUMMARY
Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are described herein. The diffusion barrier layer can protect the bottom cell plate, any underlying access transistor and even the surface of the surrounding insulating layer during processing including pre-treatment, formation and post-treatment of the capacitor dielectric layer. The diffusion barrier layer inhibits or impedes diffusion of species that may cause damage to the bottom plate or an underlying transistor, such as oxygen-containing species, hydrogen-containing species and/or other undesirable species, such as fluorine-containing species or chlorine-containing species. The diffusion barrier layer is formed separate from the capacitor dielectric layer. This facilitates thinning of the dielectric layer as the dielectric layer need not provide such diffusion protection. Thinning of the dielectric layer in turn facilitates higher capacitance values for a given capacitor surface area.
For one embodiment, the invention provides a semiconductor container capacitor structure. The semiconductor container capacitor structure includes a bottom plate overlying sidewalls and a closed bottom of a container hole, wherein the sidewalls of the container hole are defined by a surrounding insulating layer. The structure still further includes a dielectric layer overlying the bottom plate and a top plate overlying the dielectric layer. The structure further includes a diffusion barrier layer overlying at least a portion of a surface of the insulating layer adjacent the container hole. The diffusion barrier layer may be interposed between the upper surface of the insulating layer and dielectric layer or interposed between the dielectric layer and the top plate. For a further embodiment, the diffusion barrier layer contains a silicon-based material. For still further embodiments, the diffusion barrier layer contains a material having a diffusion rate for one or more oxygen-containing species, hydrogen-containing species, fluorine-containing species and/or chlorine-containing species that is lower than a diffusion rate for such species through the insulating layer.
For another embodiment, the invention provides a semiconductor container capacitor structure. The structure includes a container hole having sidewalls, an open top and a closed bottom, wherein the sidewalls of the container hole are defined by a surrounding insulating layer and wherein the open top of the container hole is defined by an upper surface of the insulating layer. The structure further includes a first conductive layer overlying the sidewalls and closed bottom of the container hole and a diffusion barrier layer overlying the upper surface of the insulating layer. The structure still further includes a dielectric layer overlying the first conductive layer and the diffusion barrier layer and a second conductive layer overlying the dielectric layer. A majority of the surface area of the first conductive layer is substantially devoid of the diffusion barrier layer.
For yet another embodiment, the invention provides a semiconductor container capacitor structure. The structure includes a container hole having sidewalls, an open top and a closed bottom. The sidewalls of the container hole are defined by a surrounding insulating layer and the open top of the container hole is defined by an upper surface of the insulating layer. The structure further includes a first conductive layer overlying the sidewalls and closed bottom of the container hole and a dielectric layer overlying the first conductive layer and the upper surface of the insulating layer. The structure still further includes a diffusion barrier layer overlying a first portion of the dielectric layer overlying the upper surface of the insulating layer and leaving a remaining portion of the dielectric layer substantially uncovered by the diffusion barrier layer. The remaining portion o

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