Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-08-02
2003-03-11
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185290, C365S185330, C365S185050, C365S185180, C365S185280
Reexamination Certificate
active
06532170
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuit memory technology. More specifically, the present invention provides a static nonvolatile memory cell for storing data.
Memory cells are used in the implementation of many types of electronic devices and integrated circuits. These devices include microprocessors, static random access memories (SRAMs), erasable-programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), Flash EEPROM memories, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), among others. Memory cells are used to store the data and other information for these and other integrated circuits.
As integrated circuit technology and semiconductor processing continue to advance, there is a need for greater densities and functionality in integrated circuits, which are often determined in a large part by the size of the memory cells. Further, it is desirable that the memory cells have improved operating characteristics, such as lower power consumption, nonvolatility, greater device longevity, improved data retention, better transient performance, superior voltage and current attributes, and improvements in other similar attributes.
Furthermore, improved memory cells are especially needed for particular applications, such as PLD integrated circuits. PLDs are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs, PLDs, EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic™, and MAX® 5000, MAX® 7000, and FLEX® 8000 EPLDs made by Altera Corp.
PLDs are generally known in which many logic array blocks (LABs) are provided in a two-dimensional array. LABs contain a number of individual programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs and LEs. The configuration of the LABs, LEs, and interconnections between these logical elements is stored in memory cells. Memory cells may be used to programmably control the composition, configuration, and arrangements of logic array blocks (LABs) and logic elements (LEs) and also the interconnections between these logic array blocks and logic elements.
Resulting from the continued scaling and shrinking of semiconductor device geometries which are used to form integrated circuits (also known as “chips”), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. Furthermore, as the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks. Also as PLDs increase in size and complexity, greater numbers of memory cells are required on to hold the configuration information of the logical elements.
While such devices have met with substantial success, such devices also meet with certain limitations, especially in situations in which the provision of more complex logic modules and additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuitry and programming complexity. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules. Moreover, there is a need to more efficiently and effectively store the configuration information of PLDs. The memory technology used to store the configuration information of the PLD should be compact, power efficient, programmable and nonvolatile, require little additional programming circuitry overhead, and generally provide enhancements to the performance and features of PLD logic modules and interconnections.
As can be seen, an improved memory cell is needed, especially an improved memory cell for storing the configuration information for the logic elements and interconnections of a programmable logic device.
SUMMARY OF THE INVENTION
The present invention provides a static, nonvolatile, and programmable memory cell for storing data in an integrated circuit. The memory cell of the present invention includes a programmable memory element. The programmable memory element is coupled between a voltage source, such as VDD or VSS, and an output node. The programmable memory element may be fabricated using many different memory technologies, including antifuse, EPROM, EEPROM, and Flash EEPROM, to name a few. In one embodiment, the programmable memory element is coupled between VDD and the output node. A pull-down device is coupled between VSS and the output node. In another embodiment, the programmable memory element is coupled between VSS and the output node. A pull-up device is coupled between VDD and the output node. The pull-down or pull-up device may be a resistor, among other devices, which may be formed using diffusion polysilicide, polysilicon, thin-film transistor, or other structure or material.
Operation of the invention when the programmable memory element is coupled between VDD and the output node is as follows. When the programmable memory element is erased, the memory cell stores and outputs a logic high at the output node. When the programmable memory element is programmed, the memory cell stores and outputs a logic low at the output node. A logic high output from the memory cell is about VDD and a logic low output is about VSS. More specifically, when the programmable memory element is programmed, a first pull-down current, or standby pull-down current, to VSS through the pull-down device will pull the output node to about VSS. Except for leakage currents, the first pull-down current may be about zero microamps. In this state, the memory cell consumes no static power.
When the programmable memory element is erased, the output node will be coupled through the programmable memory element to VDD. A second pull-down current to VSS through the pull-down device will be drained through the programmable memory element to VSS. The output node will be at about VDD. The second pull-down current may be much less than one microamp. Operation of the invention when the programmable memory element is coupled between the output node and VSS would be analogous to this discussion.
In an embodiment of the present invention, the resistance of the pull-down device is substantially less than the off resistance of the programmable memory element when the programmable memory element is programmed. The resistance of the pull-down device is substantially more than the on resistance of the programmable memory element when the programmable memory element is erased.
The memory cell of the present invention is extremely compact. The layout of the memory cell is compact. The memory cell has extremely low power consumption. A plurality of memory cells of the present invention has relatively low power consumption. The memory cell may be used to store the configuration information for a programmable logic device.
More specifically, the memory cell of the present invention includes: an output node, for providing approximately full-rail output voltages; and a pull-down device, coupled between a first voltage source at a first voltage level and the output node. The pull-down device provides
Madurawe Raminda U.
Sansbury James D.
Altera Corporation
Townsend and Townsend / and Crew LLP
Tran Andrew Q.
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