Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-10-15
2003-04-15
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S776000, C257S780000, C257S048000
Reexamination Certificate
active
06548907
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a fabrication process of a semiconductor device having a matrix array of contacts including a pin grid array or a ball grid array and a fabrication process thereof.
With the advancement in the art of device miniaturization, recent highly integrated LSI chips generally carry a very large number of contact electrodes thereon for external interconnection. For example, there are LSI chips that carry the contact electrodes with a number of several hundreds or even one thousand.
FIG. 1A
shows an example of such an LSI chip
1
of the so-called BGA (ball grid array) type in which a number of solder balls
30
are provided on a principal surface la thereof in a row and column formation as the contact electrodes. There are LSI chips of this type in which the number of the solder balls
30
exceeds 500. The solder balls
30
on the chip
1
includes power supply terminals
31
and input/output terminals
32
.
It should be noted that the fabrication process of a semiconductor device such as an LSI chip
1
includes a testing process of the chip
1
, wherein the testing process includes the step of mounting the LSI chip
1
on a testing board in the state that the solder balls
30
are connected electrically to test terminals on the testing board via corresponding contact pins. In the case of recent LSI chips carrying a very large number of solder balls
30
on the chip principal surface
1
a
, it should be noted that the number of the solder balls
30
can exceed the number of the test terminals provided on the testing board, and there arises a problem in that the testing is not possible for all of the solder balls
30
on the chip
1
.
In order to overcome the shortcomings of such a conventional testing process, it is proposed to carry out the testing process according to the process shown in the flowchart of FIG.
2
.
Referring to
FIG. 2
, a number of regions R
1
-R
4
are defined in the step S
21
on the principal surface
1
a
of the LSI chip
1
by boundaries L
1
and L
2
as indicated in
FIG. 1B
, such that the number of the solder balls
30
does not exceed the number of the test terminals of the testing board in any of the regions R
1
-R
4
. As will be explained later in detail, the test of the LSI chip
1
is conducted for each of the regions R
1
-R
4
, while the regions R
1
-R
4
are defined arbitrary. This means that the number or arrangement of the solder balls
30
as well as the type of the terminals provided by the solder balls may be different in each of the regions R
1
-R
4
.
Next, one of the regions R
1
-R
4
is selected for testing in the step S
22
, and a testing board
2
a
for the region R
1
is mounted on a testing apparatus in the step S
22
b
, as will be explained with reference to FIG.
3
A. Further, a test program corresponding to the selected region is loaded in the step S
23
on a computer cooperating with the testing board.
After the step S
23
, the LSI chip
1
is mounted on the testing board in the step S
24
.
FIGS. 3A and 3B
show the examples of mounting the LSI chip
1
on the testing board
2
a
in a bottom view, wherein
FIG. 3A
shows the LSI chip
1
mounted on the testing board
2
a
while
FIG. 3B
shows the LSI chip
1
mounted on a testing board
2
b.
Referring to
FIG.3A
, the testing board
2
a
carries thereon test terminals
33
corresponding to the power terminals
31
or the input/output terminals
32
on the selected region R
1
of the LSI chip
1
, along a periphery of the testing board
2
a
in electrical connection with contact pins that are provided on the testing board
2
a
or
2
b
in rows and columns in correspondence to the solder balls
30
on the LSI chip
1
, and the testing is conducted in the step S
25
in the state of
FIG. 3A
while using the test program loaded in the test computer previously in the step S
23
of FIG.
2
. In
FIG. 3A
, it should be noted that the contact pins on the testing board
2
a
are connected to respective, corresponding test terminals
33
via a wiring pattern
34
.
Based on the result of the testing in the step S
25
, a discrimination step S
26
is conducted for discriminating whether or not the tested region R
1
of the LSI chip
1
is defect-free, and if the result is NO, the chip
1
is discarded in the step S
27
.
Next, in the step S
28
, a discrimination is made whether or not all the LSI chips
1
are tested, and if the result is NO, the tested LSI chip
1
is dismounted from the testing board
2
a
and a next LSI chip
1
is mounted such that the region R
1
of the next LSI chip
1
is tested.
Further, in the step S
29
, a discrimination is made whether or not all the regions R
1
-R
4
of all the LSI chips
1
are tested, and if the result is NO, the first LSI chip
1
is mounted on the second testing board
2
b
of
FIG. 3B
for testing of the region R
2
. It should be noted that the testing board
2
b
is designed for testing the region R
2
and carries a wiring pattern
34
′ different from the wiring pattern
34
provided on the testing board
2
a
for testing the region R
1
. Thereby, the steps S
22
-S
29
are repeated for the all the regions R
2
-R
4
.
However, the foregoing testing process has a drawback in that it is necessary to provide a number of testing boards
2
a
and
2
b
in correspondence to arbitrarily defined regions R
1
-R
4
. It should be noted that the wiring pattern
34
has to be changed in each of the testing boards in correspondence to the selected regions R
1
-R
4
even though the testing boards may have the same row and column arrangement of the contact pins. Further, the testing program has to be changed in each of the regions R
1
-R
4
and hence in each of the testing boards. Thereby, the cost of the testing of the LSI chip increases inevitably.
Further, the foregoing testing process has a drawback in that it requires a large number of testing steps including loading and unloading of the testing programs, mounting and dismounting of the LSI chips, and the like.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device and a fabrication process thereof wherein the number of testing steps for testing the fabricated semiconductor device is reduced.
Another object of the present invention is to provide a semiconductor device and a fabrication process thereof wherein the number of testing boards used for testing the fabricated semiconductor device is reduced.
Another object of the present invention is to provide a semiconductor device and a fabrication process thereof wherein the number of testing programs used for testing the fabricated semiconductor device is reduced.
Another object of the present invention is to provide a semiconductor device, comprising:
a semiconductor chip; and
a plurality of contact electrodes provided on a principal surface of said semiconductor chip, said plurality of contact electrodes carrying signals of respective types, said plurality of contact electrodes being disposed on said principal surface of said semiconductor chip such that a first contact electrode included in said plurality of contact electrodes and carrying a signal of a first type is disposed symmetrically with respect to a second contact electrode included in said plurality of contact electrodes and carrying a signal of said first type about a hypothetical center of axial symmetry located on said principal surface of said semiconductor chip.
Another object of the present invention is to provide a method of fabricating a semiconductor device including a step of testing said semiconductor device, said step of testing comprising the steps of:
defining, in a principal surface of a semiconductor chip forming said semiconductor device, a plurality of regions each including a plurality of contact elect
Kobayashi Norihiro
Yamada Naoto
Fujitsu Limited
Ha Nathan W.
Pham Long
LandOfFree
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