Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1999-06-30
2003-03-18
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S036000, C710S059000, C710S072000, C710S313000
Reexamination Certificate
active
06535936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to data transfers over a SCSI bus, and in particular to determining the SCSI bus phase status.
2. Description of Related Art
Prior single chip parallel SCSI host adapters have included a plurality of modules and an on-chip processor that controlled operation of the modules. For example, see U.S. Pat. No. 5,659,690, entitled “Programmably Configurable Host Adapter Integrated Circuit Including a RISC Processor,” issued on Aug. 19, 1997 to Stuber et al., which is incorporated herein by reference.
A typical parallel SCSI host adapter integrated circuit
100
included a SCSI module
130
(FIG.
1
), a sequencer
120
, a data FIFO memory circuit
160
, a memory
140
, and a host interface module
110
that were interconnected by an internal chip I/O bus CIOBUS, which was used for control of host adapter integrated circuit
100
both by a host microprocessor
170
through a host adapter driver
165
and by sequencer
120
. The combination of host adapter driver
165
, sequencer
120
, and SCSI module
130
were used for controlling both synchronous and asynchronous transfers over SCSI bus
150
.
As is known to those of skill in the art, information transfer over SCSI bus
150
uses a handshake method that utilizes request signals REQs and acknowledge signals ACKs. Typically, sequencer
120
executes a sequence of instructions to perform an operation over SCSI bus
150
, and then waits for an active request signal REQ from the target device.
When host adapter
100
receives an active request signal REQ, sequencer
120
must determine the phase of SCSI bus
150
and then branch to a firmware routine that handles the SCSI bus phase. The firmware routine that handles the SCSI bus phase causes SCSI module
130
to generate an active acknowledge signal ACK on SCSI bus
150
at some point in the execution of the routine.
It is desirable to generate an active acknowledge signal as soon as possible after the active request signal REQ is received. However, there is an inherent delay associated with sequencer
120
first determining the SCSI bus phase, branching to an appropriate firmware routine, and executing the firmware routine to reach the instruction that results in assertion of acknowledge signal ACK.
Actually, the problem is somewhat more complex. The storage space for sequencer firmware in host adapter
100
is limited. Also, there are many points in the SCSI bus protocol that require sequencer
120
to wait for an active request signal REQ before proceeding. To reduce the size of the sequencer firmware associated with waiting for an active request signal REQ, determining the SCSI bus phase, and branching accordingly, many of the common sequencer instructions were located in a subroutine that was called each time it was necessary to wait for an active request signal REQ.
Within this subroutine, a sequencer firmware instruction waited for assertion of request signal REQ. After request signal REQ was asserted, the next sequencer firmware instruction waited for a possible SCSI bus parity error to be cleared by host adapter
100
. (The parity error wait instruction was necessary because there was a time delay between the occurrence of the parity error and when sequencer
120
was halted by that error. If sequencer
120
did not wait during this period, sequencer
120
could make an incorrect decision from a message byte with a bit error, and proceed down a wrong path before halting.)
After the parity error wait instruction, another sequencer firmware instruction configured a phase status byte based on the phase of the SCSI bus. After configuration of the phase status byte, the subroutine returned.
Upon return from the subroutine, subsequent sequencer firmware instructions compared an expected SCSI bus phase with the phase status byte and if a match was detected branched accordingly. Execution of the subroutine that waited for assertion of request signal REQ and the various comparisons necessary to determine the bus phase took an appreciable amount of time. However, the constraints imposed by the SCSI protocol and the storage space for sequencer firmware instructions necessitated this approach which delayed the assertion of acknowledge signal until the appropriate instruction was reached in the routine branched to based upon the comparisons.
SUMMARY OF THE INVENTION
According to the principles of this invention, a novel SCSI bus phase status register is included in a parallel SCSI host adapter integrated circuit. Initially, the SCSI bus phase status register has a predefined value. When the parallel SCSI host adapter integrated circuit must wait for assertion of a request signal by a target device, e.g., an active request signal is expected by the host adapter integrated circuit, an on-chip sequencer executes a SCSI bus phase status register read instruction. When the SCSI bus phase status register is read and has the predefined value, an active pause signal is sent to the on-chip sequencer that causes the sequencer to suspend execution of the read instruction.
When an active request signal is received from the target device, the SCSI bus phase status register is loaded automatically with a current SCSI bus phase a predefined period of time after the assertion of the request signal provided that an active parity error signal is not generated by the host adapter integrated circuit within the predefined period of time.
The loading of the SCSI bus phase status register inactivates the pause signal and so the sequencer resumes execution of the SCSI bus phase status register read instruction. Upon reading the register, the sequencer branches to a routine for the SCSI bus phase that in turn asserts an acknowledge signal if the SCSI bus phase is an expected SCSI bus phase.
Hence, this invention reduces the number of sequencer firmware instructions that must be executed prior to responding to an assertion of a request signal on the SCSI bus. Consequently, the parallel SCSI host adapter integrated circuit of this invention asserts the acknowledge signal more quickly than in the prior art host adapter integrated circuit that required execution of a complete sequence of sequencer firmware instructions prior to assertion of the acknowledge signal.
In one embodiment the parallel SCSI host adapter integrated circuit of this invention includes a memory that stores a SCSI bus phase status register read instruction. An on-chip sequencer is coupled to the memory so that the sequencer can fetch and execute the SCSI bus phase status register read instruction.
When the SCSI bus phase status register has a first value, an active signal is driven on the pause line when the SCSI bus phase status register is read by the sequencer. Upon the SCSI bus phase status register having other than the first value, an inactive signal is driven on the pause line. As used herein, all the bits in the register, a group of bits in the register, or alternatively a selected one of the bits in the registers can define the first value.
A request signal mask gate in the parallel SCSI host adapter integrated circuit of this invention includes an output terminal, and first and second input terminals. The output terminal is coupled to the SCSI bus phase status register. The first input terminal is coupled to receive a SCSI request signal. The second input terminal is coupled to a parity error line.
More specifically, a parity error sample circuit includes an input line connected to the parity error line; an enable line connected to the first input terminal of the request signal mask gate; and an output line connected to the second input terminal of the request signal mask gate. Initially, the signal on the output line to the second input terminal of the request signal mask gate is inactive. When the signal on the second input terminal of the request signal mask gate is inactive, the request signal mask gate does not pass the signal on the first input terminal therethrough.
The parity error sample circuit is enabled by the active request signal. After a
Adaptec, Inc.
Gaffin Jeffrey
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Kim Harold
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