Arrangements to reduce charging damage in structures of...

Details Arrangements to reduce charging damage in structures of... Arrangements to reduce charging damage in structures of...

2001-09-28

2003-05-20

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000, C257S328000, C257S356000, C257S360000, C257S367000

Reexamination Certificate

active

06566716

ABSTRACT:

FIELD
The present invention is directed to arrangements to reduce charging damage in structures of integrated circuits (ICs).
BACKGROUND
Although both background as well as example embodiments of the present invention will be described in the example context of charging damage phenomena with respect to gate-oxide structures of metal oxide semiconductor-field effect transistors (MOSFETs) and during plasma processing operations to manufacture an IC, practice of the present invention may not be limited thereto. For example, practice of the present invention may have uses to protect other components structures of transistors as well as structures of other components during IC manufacturing, and further, may have uses to provide protection during other (differing) IC manufacturing processing operations.
Turning now to more detailed background discussion, an IC is made up of a tremendous number (e.g., millions) of components (e.g., transistors, diodes, capacitors), with each component being made up of a number of delicate structures, e.g., MOSFET transistors have delicate gate-oxide layers. As IC manufacturing technology continues to evolve and manufacturing of smaller-and-smaller sized components and more compacted ICs become reality, the delicate structures likewise become smaller-and-smaller and more compacted, and correspondingly, more-and-more delicate.
One or more stages of manufacturing of an IC may involve plasma processing, where a semiconductor wafer (having a plurality (many tens or hundreds) of ICs in a process of being formed on a surface thereof) is subjected to charged plasma particles, gases, etc. The inventors of the present invention have learned (e.g., through analysis) that plasma processing may lead to electrical charging of exposed IC structures (e.g., metallic lines), which charging may in turn lead to damage to the aforementioned delicate structures, e.g., through excessive charge build-up, and then subsequent damaging electrical discharge. What is needed are arrangements to reduce charging damage in delicate structures of ICs.


REFERENCES:
patent: 5828119 (1998-10-01), Katsube
patent: 6034433 (2000-03-01), Beatty
patent: 6117745 (2000-09-01), Krishnan
patent: 2002/0063298 (2002-05-01), Wang

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