Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-10-11

2003-01-07

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S210130, C365S185200, C365S185210

Reexamination Certificate

active

06504778

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor memory devices such as a flash memory, an EPROM (Erasable and Programmable Read Only Memory) and a ROM (Read Only Memory), and more particularly to a semiconductor memory device of such type that data is read by comparing a data signal from a memory cell with a reference signal/reference voltage from a reference cell.
This application is based on Japanese Patent Application No. Hei 11-291663, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In general, a semiconductor memory device such as a flash memory is constructed so that multi-bit (eight-bit, for example) can be inputted and outputted. A principal structure of a read system in a semiconductor memory device of such type is shown in FIG.
8
. As shown in
FIG. 8
, a memory cell array
1100
, comprising non-volatile memory cells (not shown) arranged in a matrix, is divided into blocks
1100
-
1
to
1100
-
8
in correspondence with data bits D
0
to D
7
of external data D, respectively.
A plurality of word lines WL are arranged to extend in the row direction of the memory cell array
100
so as to pass through the blocks
1100
-
1
to
1100
-
8
with each word line being connected to control gates of those plural memory cells which belong to the same row. A plurality of bit lines BL are arranged in each block to extend in the column direction with each bit line being connected to one terminals (sources or drains) of current paths of those memory cells which belong to the same column.
The word lines WL of the memory cell array
1100
are connected to a row decoder
1200
, while the bit lines BL are connected to a column selector
1300
. The column selector
1300
is constructed such that one of the bit lines BL is selected for each of the blocks
1100
-
1
to
1100
-
8
in accordance with a column address fed from the outside.
A group of sense amplifiers
1400
comprises eight sense amplifiers of the current detection type corresponding respectively to the block
1100
-
1
to
1100
-
8
of the memory cell array
1100
and is constructed so as to detect currents of data signals which will appear on the respective bit lines selected by the column selector
1300
. Outputs Vdata-
1
to Vdata-
8
from the respective sense amplifiers in the sense amplifier group
1400
are supplied to one input parts of differential-type sense amplifiers
1501
to
1508
, respectively. The other input parts of these differential-type sense amplifiers
1501
to
1508
are supplied with a reference signal Vref which gives a reference for determining logical values of the data signals as will later be described.
A reference cell
1100
R is provided for deriving the reference signal Vref to be supplied to the above-described differential-type sense amplifiers
1501
to
1508
and is constructed comprising a plurality of reference memory cells which correspond in number to those memory cells in one row of the memory cell array
1100
. These reference memory cells are connected to a reference bit line BLR. The bit line BLR of the reference cell is connected through a reference column selector
1300
R, which is equivalent in terms of load to the column selector
1300
, to an input part of a sense amplifier of the current detection type
1400
R which corresponds to each sense amplifier in the above-described sense amplifier group
1400
.
This sense amplifier
1400
R is provided for current-detecting a signal outputted from the reference cell
1100
R to thereby supply the above reference signal Vref to the sense amplifiers
1501
to
1508
, and is designed such that a level of this reference signal Vref falls in the range between a high level and a low level of a data signal which will be outputted from each sense amplifier in the sense amplifier group
1400
as later described.
A control circuit
1700
is provided for controlling the level of the reference signal Vref in accordance with the mode of operation, For a flash memory, for example, there are provided operation modes such as a write verify mode in which the state of a memory cell into which data has been written is verified and an erase verify mode in which the state of a memory cell for which an erasure of data has been performed is verified. The levels of the reference signal Vref needed in these operation modes are different from each other.
The control circuit
1700
is to adjust the reference cell to a predetermined threshold value in the manufacturing stage of the device. This adjustment to the threshold value is carried out in such a manner that, after the initial erasure of the reference cell, a writing operation thereto is repeated until the threshold value of the reference cell reaches the predetermined threshold value.
More specifically, in order to erase the reference cell a negative voltage of about −16 volts is first applied, for example, to its gate with its source, drain and substrate being applied with a voltage of zero volt to expel electrons from a floating gate in the direction of the substrate in accordance with the FN (Fowler-Nordheim) tunneling method. Thereafter, a positive voltage of about 12 volts is applied, for example, to the gate with the drain being applied with a voltage of about six volts and with the source and substrate being applied with a voltage of zero volt to perform a write operation by injecting electrons into the floating gate in accordance with the CHE (Channel Hot Electron) method.
Thereafter, it is verified whether the correct threshold value has been obtained (write verify) by detecting the current flowing through the reference cell in the condition that a voltage of 3 volts is applied to the gate with the drain and source being applied respectively with voltages of 1 volt and zero volt. If electrons have been injected excessively an erase operation is carried out while a rewrite operation is carried out if electrons lack, depending on the result of the verification. The above process is repeated until the threshold value of the reference cell reaches the predetermined threshold value.
In general, an erase verify and a write verify are carried out with the sensitivity of the sense amplifier
1400
R being changed over, More specifically, a load transistor
1401
R shown in
FIG. 9
(which will later be described) is constructed with a plurality of transistors whose gates and drains are connected in parallel and whose sources are connected to a supply voltage (Vdd) by switching transistors interposed therebetween. By controlling on/off states of the switching transistors, a resistance value of this load transistor and hence the level of the reference signal can be changed.
Although not shown, the above-described control circuit is provided not only for the reference cell but also for the sense amplifiers
1400
-
1
to
1400
-
8
one by one to generate various voltages for the read, write, erase and verify operations.
FIG. 9
shows, as an example, a more specific circuit structure of the read system for data D
0
.
In
FIG. 9
, the block
1100
-
1
is that one of the blocks
1100
-
1
to
1100
-
8
forming the memory cell array
1100
which comprises the memory cells for storing data corresponding to data D
0
. This block
1100
-
1
comprises non-volatile memory cells
1100
M-
1
arranged in a matrix to which a plurality of word lines WL and a plurality of bit lines BL-
1
are connected. A driver
1200
D is a driver for driving the word lines WL and constitutes an output stage of the row decoder
1200
. The driver
1200
D is constructed with CMOS (Complementary Metal Oxide Semiconductor) inverters each having an input part and a source of a p-type transistor which are supplied with a respective one of pre-decoded row address signals.
A selector
1300
-
1
forms a part of the column selector
1300
shown in
FIG. 8
, which part serves to select one of the plurality of bit lines BL-
1
of the block
1100
-
1
. The selector
1300
-
1
comprises a plurality of n-type transistors one of which selectively c

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3056928