Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-26
2003-09-30
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000, C438S688000
Reexamination Certificate
active
06627541
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic devices and more particularly to an improved method utilizing a reflow operation to construct conductive interconnects and vias in a semiconductor device.
BACKGROUND OF THE INVENTION
One of the factors limiting the ability to increase the circuit density of semiconductor devices is the ability to align a conductive body in one layer to points of contact in a previously formed layer as conductive interconnections are made outwardly from the semiconductor substrate surface. Ordinarily, multiple layers of conductive materials such as aluminum, tungsten or copper are formed in layers that are separated from one another by interlevel insulative layers which may comprise, for example, silicon dioxide. The successive layers of conductive material are connected by vertical conductive bodies commonly referred to as vias.
A conductive body in a conductive layer must be aligned with the vias that it is intended to contact. Designers of integrated circuits ordinarily have to include a degree of overlap to ensure that the conductive bodies in a layer completely cover the vias they are intended to contact. This is, in part, due to the problem of “over-etching” into the via itself. If a conductive body does not completely cover the via and the material comprising the via is susceptible to being etched by the chemicals etching the conductive layer, the material within the via can be removed undesirably. If this occurs the conductive capacity of the via will be reduced potentially damaging the operation of the integrated device. However, the overlap that is included as a safety margin reduces the potential density of the integrated device.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a method of manufacturing vias and conductive layers within an integrated semiconductor device which allows for maximum device density but addresses the potential harm to the conductive capacity of vias within the structure.
In accordance with the teachings of the present invention, a method of constructing conductive vias and conductive interconnect layers is described which substantially reduces problems associated with prior methods of instruction.
According to one embodiment of the present invention, a method of constructing a semiconductor device is disclosed which comprises a step of forming a conductive via outwardly from the surface of a semiconductor substrate. A conductive interconnect body is then formed outwardly from the conductive via and electrically coupled to the conductive via. The combined structure is then subjected to a reflow heating operation to allow the material within the conductive via and the conductive interconnect to reflow in order to reduce the effect of any over etch of the via during the creation of the conductive interconnect layer.
An important technical advantage of the present invention inheres in the fact that it addresses the potential damage to the conductive via during the creation of the conductive interconnect. This reflow step allows for the conductive properties of the via to be enhanced. Due to the inclusion of this step, the overlap of the interconnect and the via may be reduced thereby increasing the overall density of the integrated device.
REFERENCES:
patent: 5288665 (1994-02-01), Nulman
patent: 5897370 (1999-04-01), Joshi et al.
patent: 6319859 (2001-11-01), Tran
patent: 6399486 (2002-06-01), Chen et al.
Brady III W. James
Coleman William David
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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