Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-11
2003-04-01
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000
Reexamination Certificate
active
06541827
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an insulated gate type semiconductor device such as a vertical MOSFET or an insulated gate bipolar transistor (IGBT), more particularly, to an insulated gate type semiconductor device of which switching time can be shorter by having a smaller gate capacitance without increasing the gate line resistance.
BACKGROUND OF THE INVENTION
A conventional vertical diffusion MOSFET (VMOSFET) has, for example, a structure as shown in FIG.
4
(
a
). That is to say, an epitaxial layer is grown on, for example, an n
+
-type semiconductor substrate
21
a
to be an n-type semiconductor layer (an epitaxial growth layer)
21
, which will later work as a drain region. On the surface of the epitaxial growth layer
21
, a p-type impurity is diffused to form a p-type body region (a cell)
22
. On the surface of the body region
22
, an n
+
-type source region
23
is formed. A gate electrode
25
is provided above the edge of the body region
22
and part of the semiconductor layer
21
outside the edge through gate oxide
24
intervened in-between. And a source electrode
26
is formed from aluminum or the like in contact with the source region
23
, and a drain electrode
27
is formed on the backside of the semiconductor substrate
21
a
, so that the edge of the body region
22
becomes a channel region
28
between the drain region (the semiconductor layer)
21
and the source region
23
, with a gate electrode
25
provided on top through the gate oxide
24
, which controls a transistor constructed of them to be turned on and off.
FIG.
4
(
a
) is a section view of a portion (one transistor cell) of a device where channel regions
28
are formed around outside of the source regions
23
, which in turn formed around one body region
22
. Actually, however, this body region
22
is an element of a matrix, which is partially shown in a plan view illustrated in FIG.
4
(
b
). In the matrix, many transistor cells are formed to construct a power MOSFET for dealing with a heavy current.
FIG.
4
(
b
) is a plan view of a portion of a device condition where the gate electrode
25
is provided before the source electrode
26
is provided. As shown in FIG.
4
(
b
), the gate electrode
25
is provided on the entire surface surrounding the p-type body regions
22
. In case the gate electrode
25
is provided on the entire surface except for contact parts of the source electrodes
26
in this manner, an input capacitor C
iss
and a feedback capacitor C
rss
are formed between the gate electrode
25
and the drain region (the semiconductor layer)
21
, causing a problem that the switching time is long when a switching operation is carried out.
To reduce such a gate capacitance, an idea is conceived that part of the gate electrode over the drain region is removed. For example, in the Japanese Unexamined Patent Publication No. 6-318705 (1994), a method for reducing the input capacitance is disclosed wherein, the gate electrode is formed and remained only above the channel regions while the rest part is completely removed, or as shown in
FIG. 5
, in review of the difficulty with forming gates only above the channel regions precisely, the gate electrode is partially removed between rows of cells
22
in array to form stripes
30
so that the gate electrode which faces the drain region is decreased to 22-70%.
As described above, from the point of view of only reducing the capacitance between the gate electrode and drain region, the capacitance can be reduced by removing part of the gate electrode. When the electrode is removed in stripes as shown in
FIG. 5
, however, there occurs a problem that part of the gate electrode for each cell can not be supplied with an equal voltage because of a serial resistance increased by the electrical connections to a part of the gate electrode for each cell from either end of each row of cells in array, since the gate electrode for a plurality of transistor cells adjoining each other is separated line by line.
SUMMARY OF THE INVENTION
The present invention is to solve the above mentioned problems, hence, it is a purpose of the invention to provide an insulated gate type semiconductor device wherein the gate of each transistor cell can be supplied with an equal voltage, and a quick switching speed is gained by reducing the gate capacitance while prevention an increase of the gate resistance.
An insulated gate type semiconductor device according to the present invention comprises:
a plurality of transistor cells, each of which comprising; a first conductivity type semiconductor layer, a body region comprising a second conductivity type diffusion region provided on the surface of the semiconductor layer, a first conductivity type diffusion region formed on the surface of the body region, a channel region formed on the surface of the body region between the first conductivity type diffusion region and the first conductivity type semiconductor layer; the plurality of transistor cells being formed regularly in the first conductivity type semiconductor layer; and
a gate electrode provided on the surface of the semiconductor layer through an insulator film so as to cover at least the surface of the channel regions; the gate electrode being patterned to have a certain shape by removing portions above where adjoining three or four of the transistor cells are bordering on each other via a point without including any part of the channel regions.
The portion where adjoining three or four of the transistor cells are bordering on each other via a point means a point of meeting of three or four transistor cells, that is, in case the transistor cells are formed by arranging them in a matrix, the adjoining four transistor cells are bordering on each other through a point where all of the four corners meet, in case the cells are arranged in array, every other row of which is shifted by half a pitch, as shown in
FIG. 3
, adjoining three of the transistor cells are bordering on each other through a point where all of the three angles meet in case the transistor cells are a hexagon, and adjoining three of the transistor cells are bordering on each other through a point where two angles meet on one side in case the transistor cells are quadrilateral. A shape of the transistor cells are determined in accordance with the shape of the body regions so that each of the body region are spaced equally.
By having this structure, the gate electrode is removed in portions which are away from the channel regions of the transistor cells, therefore, it is easy to arrange the removed portions of the gate electrode so that each of them is not overlapped with any part of the channel regions. And parts of the gate electrode for the respective transistor cells are connected to each other to form the gate electrode, so that nothing interferes with the signal supplied to the gate electrode covering each of the channel regions for the transistor cells, and the voltage is supplied to the gate electrode for each of the transistor cells with a low resistance. On the other hand, the capacitance between the gate electrode and the drain region is lowered by the eliminated area of the gate electrode, which can maintain the switching speed very fast.
More concretely, the plurality of transistor cells are arranged in array, every other row of which is shifted by half a pitch from the adjacent row, the body regions and the transistor cells form a quadrilateral or a hexagon on the surface (on a plane form), and the gate electrode is removed in portions above where adjoining three of the transistor cells are bordering on each other, or the plurality of transistor cells are arranged in a matrix, the body regions and the transistor cells form a quadrilateral on the surface(on a plane form), and the gate electrode is removed in portions above where adjoining four of the transistor cells are bordering on each other. By those structures, a high speed of switching can be achieved without increasing the gate resistance and by reducing the capacitance between the gate elect
Arent Fox Kintner Plotkin & Kahn
Loke Steven
Owens Douglas W.
Rohm & Co., Ltd.
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