Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-06-24
2003-04-01
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S164000, C438S622000, C438S637000, C438S672000
Reexamination Certificate
active
06541314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with a SOI structure and a method of manufacturing the same.
2. Description of the Related Art
The substrate structure of a chip of a semiconductor device of the present invention is not limited in particular. However, the present invention is applied to a so-called SOI (Silicon On Insulator) which is the most popular structure. The SOI structure is formed by use of the techniques such as a SIMOX (Separation by Implanted Oxygen) method using ion implantation of oxygen ions, and a method of bonding silicon substrates. For example, as a chip
110
shown in
FIG. 1A
, the structure is formed in which an insulating film
303
and a single crystal semiconductor layer
302
are formed in this order on a support substrate
301
usually made of a silicon substrate.
The semiconductor device using the substrate having the SOI structure (hereinafter, referred to as an SOI semiconductor device) is preferable for the application requiring a high breakdown voltage. In the SOI semiconductor device, a chip is typically mounted on an island of a-package by conductive adhesive, and an external connection electrode on the chip are individually connected to predetermined external terminals by use of a wire bonding method, similarly to a typical semiconductor device. The island is connected to any of the external terminals, which is a ground terminal in many cases. In this case, the support substrate can be connected through the island to the ground.
In the SOI semiconductor device, a mounting method or an assembling method such as a chip-on-board method using a flip chip (hereinafter, referred to as COB method) or a tape carrier package (hereinafter, referred to as TCP) method is employed for a higher density mounting method. In this case, as shown in
FIGS. 1A and 1B
the external connection electrode (not shown) provided on the single crystal semiconductor layer
302
of the chip
110
and a conductive wiring
71
of a wiring substrate
70
to be mounted or an inner lead
80
of TCP are connected to each other through a bump
201
. Therefore, there is a problem that it is difficult to apply a potential to the support substrate
301
.
If the support substrate is in a floating potential, a potential variation in the support substrate has an adverse influence on an operation of an element, in particular, a threshold potential. As a result, an operation margin of the element is reduced. Also, as disclosed in Japanese Patent No. 2654268, Japanese Laid Open Patent Application (JP-A-Heisei 8-153781) or Japanese Laid Open Patent Application (JP-A-Heisei 8-236754), the breakdown voltage of the element changes depending on the potential of the support substrate. Therefore, if the potential of the support substrate is varied during the operation of the semiconductor element, the breakdown voltage of the element decreases so that there is a possibility of the occurrence of an erroneous operation.
As a method of avoiding the support substrate from being in the floating state, for example, Japanese Laid Open Patent Application (JP-A-Heisei 6-244239) (hereinafter, referred to as a conventional example 1) discloses an example of an SOI semiconductor device in which a potential can be applied from a surface of an element side to the support substrate.
FIG. 2
is a sectional view showing the semiconductor device disclosed in the conventional example 1. With reference to
FIG. 2
, a semiconductor layer
703
of the semiconductor device disclosed in the conventional example 1 is insulated from a semiconductor substrate
701
by an intervening layer insulating film
702
. However, conductors
710
are provided on side walls of a concave portion
709
to extend to the semiconductor substrate
701
so that a short-circuit is formed between the semiconductor substrate
701
and a peripheral region
703
b
. Thus, the same potential as that of the peripheral region
703
b
is applied to the semiconductor substrate
701
. The potential is applied to the peripheral region
703
b
through a bump
707
from a wiring substrate (not shown), similarly to an element formation region. That is, the potential is applied to the semiconductor substrate
701
from the surface side of the semiconductor layer
703
on which the element is formed.
Also, Japanese Laid Open Patent Application (JP-A-Heisei 2-54554) (hereinafter, referred to as a conventional example 2) discloses a structure in which a semiconductor device is manufactured by use of an SOI substrate and separated into elements by an embedded insulating film. In the conventional example 2, a conductive substrate is used as a lower layer of an insulating film constituting the SOI structure.
FIG. 3
is a sectional view showing a main portion of the semiconductor device shown in the conventional example 2. With reference to
FIG. 3
, the semiconductor device disclosed in the conventional example 2 has a structure in which an insulating film
802
and a conductive semiconductor layer
803
are bonded in this order on a conductive substrate
801
. An element body
804
is formed in the semiconductor layer
803
. An element separation trench
805
is provided to contact the insulating film
802
at its bottom and to surround the element body
804
. The element separation trench
805
is filled with a fill material
814
made of an insulator or polysilicon. The fill material
814
contains therein a conductive fill material
851
made of a p-type polysilicon layer reaching the insulating film
802
from the surface of the element separation trench
805
. An opening
821
is formed in the insulating film
802
to connect the conductive fill material
851
and the conductive substrate
801
. In the semiconductor device in the conventional example 2, the conductive substrate
801
and an electrode
807
provided on the surface of the fill material
814
are connected by the conductive fill material
851
. Thus, the conductive substrate
801
can be used as the conductive material. Therefore, it is possible to reduce the crowded condition of surface wiring lines.
In the semiconductor device of the conventional example 1, the formation of a trench for the element separation region and the formation of a concave trench for a substrate contact are independently carried out as the different processes. Therefore, it is necessary to etch and remove the semiconductor layers
703
at the different positions of the SOI substrate two times. As a result, there is a problem that the manufacturing process becomes long. Also, the structure is designed in such a manner that the route connecting a bump electrode
707
for applying the potential to the support substrate and the support substrate
701
must pass through a peripheral region
703
b
of the semiconductor layer. Thus, there is another problem that the drop of the resistance in the route is limited.
Also,in the method of manufacturing the semiconductor device in the conventional example 2, a first trench as the trench for the element separation and a second trench having the width wider than that of the first trench are formed at the same time. Also, the insulating film
802
in the bottom of the second trench is etched so that the opening
821
is formed to reach the conductive substrate corresponding to the support substrate
801
. In this case, a multi-layer film in which a polysilicon film, a nitride film and an oxide film are laminated is required so as not to etch the other regions. Also, the conductive fill material
851
is formed to connect the electrode
807
and the conductive substrate
801
by implanting impurities such as boron into an insulating polysilicon layer. Thus, there is a limit on the drop in the resistance.
It should be noted that Japanese Laid Open Patent Application (JP-A-Heisei 11-135794) discloses the following semiconductor device. In this reference, the semiconductor device has the CMOS structure in which a pair of offset type MOS transistors of a first conductive type and a second conductive type are
Quach T. N.
Scully Scott Murphy & Presser
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