Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-11-09
2003-04-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S605000, C438S592000
Reexamination Certificate
active
06555456
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention is generally related to the fabrication of integrated circuits (ICs) and, more specifically, to the fabrication of a conductive barrier using iridium (Ir) and tantalum (Ta), for use as an electrode in a ferroelectric device.
Platinum (Pt) and other noble metals are used in IC ferroelectric capacitors. The use of noble metals is motivated by their inherent chemical resistance. This property is especially desirable under high temperature oxygen annealing conditions, such as those seen in the fabrication of ferroelectric capacitors. In addition, chemical interaction between noble metals and ferroelectric materials such as perovskite metal oxides, is negligible.
Specifically, the above-mentioned noble metals are used as conductive electrode pairs separated by a ferroelectric material. One, or both of the electrodes are often connected to transistor electrodes, or to electrically conductive traces in the IC. As is well known, these ferroelectric devices can be polarized in accordance with the voltage applied to the electrode, with the relationship between charge and voltage expressed in a hysteresis:loop. When used in memory devices, the polarized ferroelectric device can be used to represent a “1” or a “0”. These memory devices are often called ferro-RAM, or FRAM. Ferroelectric devices are nonvolatile. That is, the device remains polarized even after power is removed from the IC in which the ferroelectric is imbedded.
There are problems in the use of metal, even noble metal electrodes. Pt, perhaps the widely used noble metal, permits the diffusion of oxygen, especially during high temperature annealing processes. The diffusion of oxygen through Pt results in the oxidation of the neighboring barrier and substrate material. Typically, the neighboring substrate material is silicon or silicon dioxide. Oxidation can result in poor adhesion between the Pt and neighboring layer. Oxidation can also interfere with the conductivity between neighboring substrate layers. Silicon substrates are especially susceptible to problems occurring as a result of oxygen diffusion. The end result may be a ferroelectric device with degraded memory properties. Alternately, the temperature of the IC annealing process must be limited to prevent the degradation of the ferroelectric device.
Various strategies have been attempted to improve the interdiffusion, adhesion, and conductivity problems associated with the use of noble metals as a conductive film in IC fabrication. Titanium (Ti), titanium oxide (TiO
2
), and titanium nitride (TiN) layers have been interposed between a noble metal and silicon (Si) substrates to suppress the interdiffusion of oxygen. However, Ti layers are generally only effective below annealing temperatures of 600 degrees C. After a 600 degree C. annealing, Pt diffuses through the Ti layer to react with silicon, forming a silicide product. Further, the Pt cannot stop the oxygen diffusion. After a high temperature annealing, a thin layer of silicon oxide may be formed on the silicon surface, which insulates contact between silicon and the electrode.
Other problems associated with the annealing of a Pt metal film are peeling and hillock formation. Both these problems are related to the differences in thermal expansion and stress of Pt with neighboring IC layers during high temperature annealing. A layer of Ti overlying the Pt film is known to reduce stress of the Pt film, suppressing hillock formation.
Ir has also been used in attempts to solve the oxygen interdiffusion problem. Ir is chemically stable, having a high melting temperature. Compared to Pt, Ir is more resistant to oxidation and oxygen diffusion. Further, even when oxidized, iridium oxide remains conductive. When layered next to Ti, the Ir/Ti barrier is very impervious to oxygen interdiffusion. However, Ir can diffuse through Ti. Like Pt, Ir is very reactive with silicon or silicon dioxide. Therefore, a bilayered Ir/Ti or Ir/TiN barrier is not an ideal barrier metal.
Co-pending application Ser. No. 09/263,970, entitled “Iridium Composite Barrier Structure and Method for Same”, invented by Zhang et al., and filed on Mar. 5, 1999, discloses a Ir composite film that is resistant to interdiffusion.
It would be advantageous if a method were developed for the use of Ir as a conductor, conductive barrier, or electrode in IC fabrication. It would be advantageous if the Ir could be used without interaction to an underlying Si substrate.
It would be advantageous if Ir film could be layered with an interposing film to prevent the interaction of Ir with a silicon substrate. It would be advantageous if the multilayered film including a layer of Ir could resist the interdiffusion of oxygen at high annealing temperatures. It would also be advantageous if the multilayered film including Ir was not susceptible to peeling problems and hillock formation.
Accordingly, a conductive barrier or electrode is provided comprising an underlying silicon substrate, a first barrier film including tantalum (Ta) overlying the substrate, and an iridium (Ir) film, having a thickness in the range of approximately 20 to 200 nanometers (nm), overlying the first barrier film. The combination of the Ir film and the first barrier film is resistant to the interdiffusion of oxygen into the silicon. In some aspects of the invention, a titanium (Ti) film overlies the Ir film. The Ti layer has a thickness in the range of approximately 5 to 25 nm. The Ti film suppresses the formation of hillock regions at high annealing temperatures.
The first barrier film is selected from the group of materials consisting of Ta and tantalum nitride (TaN), and has a thickness in the range of approximately 10 to 100 nanometers (nm).
In some aspects of the invention, a second barrier layer is interposed between the first barrier layer and the silicon substrate. Typically, the first barrier layer is TaN and the second barrier layer is Ta. The first and second barrier layers have a combined thickness in the range of approximately 20 to 200 nm, with the second barrier layer thickness being in the range of approximately 10 to 100 nm.
The above-described conductive barrier is well suited to the formation of ferroelectric devices, where the conductive barrier acts as at least one of the electrodes. Then, a ferroelectric film overlies the Ir film, and a conductive metal film, which can be a multilayered film, overlies the ferroelectric film. In this manner, the ferroelectric film can be annealed at high temperatures in an oxygen ambient conditions to enhance its memory related charge storage characteristics.
A method for forming a highly temperature stable conductive barrier overlying an integrated circuit substrate is also provided. The method comprising the steps of:
a) depositing a first barrier layer including tantalum (Ta) overlying the substrate; and
b) depositing an iridium (Ir) film overlying the first barrier layer, whereby a multilayer structure is formed that is resistive to interaction with the substrate.
Optionally, a further step, follows Step b), of:
c) depositing a layer of titanium (Ti) overlying the Ir electrode, whereby the formation of hillocks is suppressed.
Step a) includes depositing the first barrier layer through deposition methods selected from the group consisting of chemical vapor deposition (CVD), physical vapor deposition (PVD), including sputtering, and metal organic CVD (MOCVD). When deposited by PVD sputtering, a 1:X flow of Ar to N
2
is used, where X is greater then, or equal to 1.
Step b) includes depositing the Ir film at a temperature in the range of approximately 200 to 500 degrees C., using deposition methods from the group consisting of PVD, CVD, and MOCVD.
In one aspect of the invention, a further step follows Step c), of:
c1) annealing the layers deposited in Steps b) and c) at a temperature in the range of approximately 600 to 800 degrees C. in atmospheric conditions selected from the group consisting of Ar and vacuum ambient.
REFERENCES:
patent: 5858182 (1999-01-01), Horng et al.
patent:
Hsu Sheng Teng
Maa Jer-shen
Zhang Fengyan
Isaac Stanetta
Krieger Scott C.
Niebling John F.
Rabdau Matthew D.
Ripma David C.
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