High frequency range four bit prefetch output data path

Details High frequency range four bit prefetch output data path High frequency range four bit prefetch output data path

2001-03-14

2003-04-29

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S189050, C365S233100

Reexamination Certificate

active

06556494

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and in particular to a data path in a memory device.
BACKGROUND OF THE INVENTION
Semiconductor memory devices such as synchronous dynamic random access memory (SDRAM) devices are widely used in computers and electronic products. A SDRAM device typically has a large number of memory cells to store the data. To read the data, a memory read operation is performed. During a read operation, data from the memory cells are accessed and output to a data pad for processing. The operation of the SDRAM is based on a common clock signal.
There are several variations of SDRAM devices. In one variation, data from the memory cells are accessed and one bit of data is output to the data pad in every clock cycle. In another variation of SDRAM devices, two bits of data are accessed and output to the data pad in every clock cycle; thus, this variation of SDRAM devices is commonly referred to as double data rate (DDR) SDRAM device.
Currently a new variation of SDRAM devices has been proposed by Joint Electronic Device Engineering Council (JEDEC), an international organization that sets standards for integrated circuit devices including memory devices. A draft of a specification for the SDRAM device proposed by JEDEC is incorporated herein as a reference. In the proposed SDRAM device or DDR II SDRAM device, four bits of data within the memory device are accessed and output to the data pad during a read cycle. Thus, a DDR II SDRAM device outputs data at a higher speed than a traditional DDR SDRAM device.
One of the challenges of operating a DDR II SDRAM device is implementing the device so that the four bits of data from the memory cells are properly output to the data pad. In a DDR SDRAM device, since a group of two bits of data are accessed at a time, two bits from one group can be output to the data pad in one clock cycle. In the next clock cycle, the next group of two bits can also be output to the data in the same fashion as the previous group. Thus, in every two clock cycles, four bits are output to the data pad; the four bits are from two different groups. In the DDR II SDRAM device, a group of four bits are accessed at a time and are output to the data pad in two clock cycles, two bits in each of the two clock cycles. However, unlike the DDR SDRAM, since the four bits are from the same group, the DDR II SDRAM device must distinguish which two of the four bits to output in which one of the two clock cycles. In addition, a proper bit order must also be determined so that each of the four bits is output to the data pad in a right order.
There is a need for an implementation in a DDR II SDRAM in which data is properly output from the memory cells to the data pad during a read operation.
SUMMARY OF THE INVENTION
The present invention is a DDR II SDRAM device having an output circuit to implement data transfer between memory cells and data pads of the memory device.
In one aspect, the memory device includes a plurality of input nodes to receive a group of M bits of data from the memory cells in parallel. N output paths are connected between the input nodes and the data pad, in which M and N are greater than two. Each of the output paths transfers a different bit of the group of M bits of data. The M bits of data are transferred to the data pad in series by activating a plurality of timing signals. The timing signals are activated by a first and a second enable signals. The enable signals are not synchronized.
In another aspect, a method of transferring data is provided. The method includes reading M bits of data in parallel to a plurality of output paths, in which M is greater than two. The method also includes transferring the M bits of data from the output paths to an output select. Each of the output paths transfers a different bit of data. The method also includes activating a first and second enable signals and a plurality of timing signals. The timing signals are activated in series based on the enable signals. The method further includes transferring the M bits of data in series to an output stage following transitions of the timing signals, and outputting the M bits of data to a data pad within two cycles of a clock signal.


REFERENCES:
patent: 5828618 (1998-10-01), Hosotani et al.
patent: 5999458 (1999-12-01), Nishimura et al.
patent: 6084823 (2000-07-01), Suzuki et al.
patent: 6324118 (2001-11-01), Ooishi
patent: 2000-076853 (2000-03-01), None
“DDR-II SDRAM Specification”,JEDEC Meeting, JC 42.3, pp. 1-43, (Sep. 2000).

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