Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-21
2003-05-20
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S664000
Reexamination Certificate
active
06566254
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor device, and more particularly to a method for forming electrodes by using a salicide technology for selectively forming a silicide film on gate electrodes and diffusion layers of MOS transistors.
2. Description of the Related Art
In salicide (self align silicide) technologies for forming a silicide film on gate electrodes and diffusion layers of MOS transistors in a self-aligning fashion, it is important that the silicide film to be formed on the gate electrodes and diffusion layers is uniform in film thickness and stable in electric resistance. This prefers to employ a salicide technology using titanium (Ti) which produces silicides having smaller specific resistances and has an appropriate Schottky barrier height to both p-types and n-types. However, when the gate electrodes and diffusion layers rise in surface impurity concentration with increasing fineness of semiconductor devices and become finer in dimension as well, the silicides with titanium increase in the temperature at which phase transition occurs from high-resistance C49 titanium disilicide (TiSi
2
) to low-resistance C54 titanium disilicide, especially on the n-type diffusion layers. Accordingly, adjusting the silicidation-annealing temperature to the n-type produces a problem in that excessive silicidation on the p-type conductive layers causes deterioration of the p-n junction leakage characteristics and aggregation of the silicide films. On the contrary, adjusting the annealing temperature to the p-type creates a problem in that insufficient silicidation on the n-type diffusion layers makes the silicide films smaller in thickness, higher in resistance, and so on. Therefore, the technology is far from being sufficient to form a silicide film on gate electrodes and diffusion layers in a self-aligning fashion.
Thus, for example, K. Goto et al, Technical Digest of IEEE International Electron Device Meeting 1995, pp.449-452 (1995) discloses a technique of selectively forming a silicide film on gate electrodes and diffusion layers in a self-aligning fashion by using cobalt (Co). This conventional technology will be described below.
FIGS. 1A through 1C
are longitudinal sectional views showing this conventional technology in the order of its steps. Initially, as shown in
FIG. 1A
, element isolation regions
102
are formed on prescribed areas of a single-conductive type silicon substrate
101
by using a LOCOS method. The element isolation regions
102
define an element forming region on which a gate oxide film
103
and gate silicon film
104
are formed. Sidewalls
105
are formed on the side surfaces of the gate silicon film
104
. Formed in said silicon substrate
101
are reverse-conductive type diffusion layers
106
serving as source and drain regions with an n+/p junction depth of 100 nm, thereby forming a MOS transistor. Thereafter, a cobalt film
107
a
is formed in a thickness of 10 nm by sputtering so as to cover said MOS transistor, followed by a titanium nitride (TiN) film
108
b
formed in a thickness of 30 nm by sputtering. The purpose of said titanium nitride film
108
b
is to prevent cobalt from being oxidized during the annealing treatments for silicidation.
Subsequently, as shown in
FIG. 1B
, first annealing is applied to the silicon substrate
101
in a nitrogen atmosphere at 550° C. for 30 seconds by ramp rapid thermal annealing method. This allows the surface portions of the gate silicon film
104
and diffusion layers
106
to react with the cobalt film
107
a,
forming cobalt silicide films
107
b
having a composition of Co
x
Si
y
(x≧y) in a self-aligning fashion.
Then, as shown in
FIG. 1C
, the titanium nitride film
108
b
and the unreacted cobalt films
107
a
remaining on the field are removed by wet etching before second annealing is applied in a nitrogen atmosphere at 750-900° C. for 30 seconds by ramp rapid thermal annealing. This transforms said cobalt silicide films
107
b
on the surfaces of the gate silicon film
104
and diffusion layers
106
into cobalt disilicide (Cosi
2
) films
107
c
which are thermally stable and low in resistance. In this technique, the use of cobalt for the silicidation metal instead of titanium can solve said problems in the higher resistances and silicide film aggregation resulting from the finer patterns and the increase in the phase transition temperature from the C49 structure to C54 structure in the regions with higher impurity concentrations.
This salicide technology, however, is to deposit a metal film over the entire surface of the silicon substrate and allow silicidation only on the silicon-exposed regions for resistance reduction, so that the silicidation inevitably involves the metal film on the insulating films lying in the vicinity of the element isolation ends and pattern edges. On this account, a problem occurs on the occasion when those metals compared to titanium and the like with higher silicon consumption in silicidation, such as cobalt, are applied to finer semiconductor devices.
More specifically, when the diffusion layers and gate electrodes become finer and finer involving decreases in the p-n junction depth of the diffusion layers, there occurs “bite of silicide” in which the silicide films
107
c
penetrate into the silicon substrate
101
at the ends of the element isolation regions
102
and beneath the sidewalls
105
on the gate-electrode side. As seen under the sidewall
105
in
FIG. 2
, the silicide films
107
c
came close to the p-n junction plane of the diffusion layers
106
, which might deteriorate characteristics such as junction leakage, isolation withstand voltage, and gate withstand voltage. In particular, diffusion layers
106
of LDD structure have thinly-formed LDD regions, which increases the danger of the deterioration. Accordingly, this technique is also far from a salicide technology that can offer an ultimate solution to the above-described problems.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for manufacturing a semiconductor device which forms in a self-aligning fashion a silicide film being low in resistance and stable in electric characteristics even on gate electrodes and diffusion layers being fine in dimension and high in impurity concentration, without deteriorating characteristics such as junction leakage, isolation withstand voltage, and gate withstand voltage.
A method for manufacturing a semiconductor device according to the present invention comprises the steps of: forming a gate electrode, sidewalls provided on both side surfaces of said gate electrode, and diffusion layers formed at a surface of a silicon substrate by a self-aligning technique within an element forming region defined by element isolation regions provided on said silicon substrate; and forming a silicide film at least on the surfaces of said diffusion layers.
The step of forming a silicide film of a first aspect of the present invention comprises the steps of: selectively forming a first metal film at least on the diffusion layers; applying first annealing thereto to allow at least said diffusion layers to react with said metal film; removing part of sidewalls to form a gap with the first metal film; and performing second annealing at a temperature higher than that of the first annealing.
Moreover, a method for forming a silicide film of a second aspect of the present invention includes the steps or: forming a first metal film on the silicon substrate having a MOS transistor formed thereon; applying first annealing thereto to allow at least the diffusion layers to react with the first metal film; selectively removing unreacted portions of the aforesaid first metal film; removing part of sidewalls to form a gap with the first metal film; and performing second annealing at a temperature higher than that of the first annealing.
Furthermore, as a third aspect of the present invention, a method for forming a silicide film according to the present in
Choate Hall & Stewart
Cuneo Kamand
Geyer Scott
NEC Electronics Corporation
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