Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
2001-09-28
2003-04-29
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S423000, C438S475000, C438S510000, C438S514000, C438S515000, C438S517000, C438S522000, C438S559000, C438S565000, C438S664000, C438S682000, C438S766000, C438S914000, C438S961000
Reexamination Certificate
active
06555451
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
This invention relates generally to the doping of a semiconductor substrate to create conductive junctions and circuits, and more specifically, relates to a method for the creation of ultra-shallow doping junctions using elemental doping.
2. Related Art
As our society has become more technology based, semiconductors have come to play a vital role. Semiconductor wafers with accompanying circuitry are commonly used in the manufacture of such everyday items as televisions, radios, and computers. The process of manufacturing semiconductors (which are commonly called chips) typically consists of more than 100 steps, during which hundreds of copies of an integrated circuit are formed on a single wafer. The wafer is commonly a silicon dioxide (SiO2) substrate with electrically conductive surface circuits patterned upon the substrate. The circuits may be of near microscopic size and thickness.
Semiconductor devices have many and varied applications in electrical engineering. Recent engineering developments have yielded extremely small semiconductor chips containing hundreds of thousands of transistors. These chips have made possible great miniaturization of electronic devices.
One of the more important steps in semiconductor manufacture is doping. Doping is the addition of elements other than silicon to provide conductivity within the circuit. P-N junctions are commonly created to assist circuit conductivity. Silicon has four valance electrons. Atoms with one valance electron less than silicon, such as boron, or one more valance electron than silicon, such as phosphorus, are introduced into an area desired for conductivity. The addition of the elements alters the electrical character of the silicon. An element with one less valance electron than silicon, usually boron, creates a “positive hole”, or P-type area, as compared to the silicon substrate. An element having one more valance electron than silicon, usually phosphorus, creates a more negative, or N-type area. Electrical conduction can take place between the N and P areas, altering the electrical character of the silicon. In other words, when the P-type and N-type semiconductor regions are adjacent to each other, the regions form a semiconductor diode, and the region of contact is called a P-N junction. A diode is a two-terminal device that has a higher resistance to electric current in one direction and a lower resistance in the opposite direction. The conductive properties of the P-N junction depends on the direction of the applied voltage, which can, in turn, be used to control the directional nature of the device. Therefore, P-N junctions can be used to direct the electrical current flow in a semiconductor in a specific direction. Series of such junctions are used to make transistors in many semiconductor devices. Such semiconductor devices include, among others, solar cells, lasers, and rectifiers.
More efficient use of semiconductor chips has been developed through what is called complementary metal-oxide semiconductor circuitry, or CMOS circuitry, formed by pairs of P and N channel transistors controlled by a single circuit.
In creating P-N junctions, the ideal is to create junctions that are as shallow as possible. The more shallow a junction can be made, yet still remain effective in conducting electricity, the more efficient will be the conduction of electricity. Conversely, the greater the diffusion of the P-N dopant into the substrate, the lower the efficiency of the conduction of electricity through the semiconductor circuit.
Shallow P+ and N+ junctions are required for future generations of VLSI transistors made on bulk silicon substrates and ultra-thin SOI, for hyperabrupt P+ junctions for Esaki tunnel diodes, for shallow P layers to control the threshold voltage of P-channel MOSFETs, and for making thin silicon layers for compliant substrates by using P+ layers as an etch stop along with a hydrogen ion implant layer splitting approach.
Two principal methods of creating shallow P-N dopant junctions upon the semiconductor surface are ion implantation and heat diffusion. In an ion implantation method, ions of the dopant are fired at the wafer surface and embedded therein. In a heat diffusion method, ions of the dopant are placed upon the surface of the wafer and diffused therein with heat. Ion implantation suffers from the limitation that the ion impacts cause damage to the surrounding silicon matrix. This damage interferes with the efficiency and conductivity of electricity conduction. Heat diffusion has a serious limitation as well. Heat diffusion tends to diffuse the dopant too greatly, reducing conductive efficiency.
Shallow junctions in silicon are commonly made by implanting ions using low implantation energy. Implant energies from 1 KeV to 10 KeV are currently being investigated for forming ultra-shallow junctions. However, impacts from ion implantation still create point defects in the semiconductor lattice that can lead to enhanced diffusion of the dopant atom making it difficult to achieve ultra-shallow junctions. To our knowledge, the shallowest junction made to date using ion implantation are on the order of 30-50 nm deep into the semiconductor.
Some attempts have been made within the art to improve the quality of semiconductor junctions. Prior art of interest in the field of doping semiconductor substrate surfaces includes U.S. Pat. No. 6,037,640 (Lee); U.S. Pat. No. 5,866,472 (Noslehi); U.S. Pat. No. 5,310,711 (Drowley et al.); U.S. Pat. No. 5,256,162 (Drowley et al.); U.S. Pat. No. 5,242,859 (Degelomo et al.); U.S. Pat. No. 5,183,777 (Doki et al.); U.S. Pat. No. 4,951,603 (Yoshino et al.); U.S. Pat. No. 4,804,438 (Rhodes); and U.S. Pat. No. 4,392,453 (Luscher). The Lee patent discloses a method for making junctions by co-implanting a non-dopant at a higher energy and at a greater depth than the dopant ion. The low energy, dopant implantation step is followed by a fast isothermal annealing step. Junctions 10-45 nanometers deep are said to be created. The Noslehi, Drowley et al. ('711 and '162) and Degelomo et al. patents each disclose thermally activated direct gas phase doping methods. The direct diffusion of the dopant gas creates heavily doped junctions. These gas phase dopant methods are said to have the potential of creating junctions at a depth of 1000 A (100 nm) or less. The Doki et al. patent discloses an implantation method which involves the formation of a dopant containing film on the surface of a silicon substrate. After the formation of the film, which is composed of hydrogen compounded with either boron, phosphorus, or arsenic, the substrate is heated to cause diffusion. This method is said to create junctions at a depth of 1000 A (100 nm) or less. The Yoshino et al., Rhodes, and Luscher patents each involve the use of vacuum systems in the production of semiconductors. The Yoshino et al. patent discloses an apparatus which deposits semiconductor layers on a substrate in a vacuum chamber. The Rhodes patent discloses a method for depositing conductive layers on silicon substrates under vacuum. The Luscher patent discloses a method for producing a semiconductor film through the use of molecular beams which coat the wafer in a vacuum system.
SUMMARY OF THE INVENTION
In accordance with the invention, a method is provided for making ultrashallow diffused junctions using an elemental dopant.
The method is comprised of the steps of cleaning a semiconductor wafer so as to provide a clean reaction surface, loading the cleaned wafer onto a stage located in a vacuum system, placing a quantity of elemental dopant atoms in a partially enclosed elemental dopant source located within a secondary vacuum enclosure, depositing a quantity of the elemental dopant atoms having thermal velocities onto the surface of the wafer, heating the wafer so as to diffuse the elemental dopant atoms into the wafer, and removing the wafer from the vacuum system.
Advantageously, the heating comprises heating the wafer in an ultra-high vacuum
Hobart Karl D.
Kub Francis J.
Cuneo Kamand
Grunkemeyer Joseph T.
Karasek John J.
Kilday Lisa
The United States of America as represented by the Secretary of
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