Reconfigurable FIFO interface to support multiple channels...

Details Reconfigurable FIFO interface to support multiple channels... Reconfigurable FIFO interface to support multiple channels...

2000-05-01

2003-07-15

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S038000, C710S036000

Reexamination Certificate

active

06594714

ABSTRACT:

TECHNICAL FIELD
The technical field is data systems that support multiple agents.
BACKGROUND
Current computer architectures may have a single microprocessor or chip that services data to multiple agents. Each agent may be allocated one or more physical channels or ports to handle the data flow. A common requirement of this design may be that the host chip maintain bandwidth requirements for all the agents in parallel. Another requirement is that data from a first agent must travel in order such that the data arriving at a point at which the first agent merges with other agents is in the same order as when the data left the first agent. In other words, data out of an agent must be provided in the same order as the data are received, even if the data are spread across multiple channels. Yet another requirement may be that two or more physical channels may be configurable as two separate logical agents, or grouped into one logical agent. The ability to group multiple channels into one agent is called bundling.
For single-channel agents, a common computer architecture provides dedicated first in/first out (FIFO) register arrays for each channel and to then multiplex the final output in whatever arbitrated fashion is desired. The circuit that supports the dedicated FEFOs must have an output bandwidth that is greater than or equal to the sum of incoming bandwidths from the channels. For example, in an architecture with four channels, each 8-bits wide, the FIFOs in the final multiplexing stage must be at least 32 bits wide to maintain the bandwidth at the same clock frequency. If frequencies differ, the same bandwidth rule applies, but the bit width may not be the sum of the channels.
Chip area considerations drive chip designers to find ways to economize area demands by reducing as much as possible the number of discrete components on the chip. In a case where two or more physical channels are maintained as one logical agent, chip area can be conserved feeding all data through a particular agent's FIFO for all physical channels bundled to that agent. The main disadvantage of this structure is that a single channel agent configuration has unnecessarily deep FEFOs for some agents, resulting in larger chip area and, therefore, a higher cost of the chip. Moreover, the multiple agent configuration does not use all the FIFOs resulting in larger chip area and cost.
SUMMARY
A reconfigurable register array structure allows data transmission from a single agent or in bundled form from multiple agents. The structure makes economical use of valuable chip space by reducing the size of the overall register array system. A coalescing prestage is used to collect data from single agents or from multiple agents and to multiplex the data, based on a priority scheme, to supply the data to a primary stage of first-in-first-out register arrays. The coalescing prestage may include one or more first registers, a delay register, and multiplexers to select outputs of the first registers.
In an alternative embodiment, the coalescing prestage may include one or more register array structures, each such structure having independent write ports, an independent write port for each agent or channel. The structure also has individual read ports. Data coalesced in the coalescing prestage is provided to the primary stage. The primary stage may include one or more logical register arrays configured on a physical array. Separate write pointers may be used to ensure data from a particular channel is provided to the correct location in the physical array.


REFERENCES:
patent: 4558433 (1985-12-01), Bernstein
patent: 6175910 (2001-01-01), Pauporte et al.
patent: 6219756 (2001-04-01), Kasamizugami
patent: 6430626 (2002-08-01), Witkowski et al.
patent: 6442724 (2002-08-01), Augarten

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