Memory cell arrays

Details Memory cell arrays Memory cell arrays

2001-12-13

2003-07-15

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06593610

ABSTRACT:

TECHNICAL FIELD
The invention pertains to memory arrays and methods of forming memory cells. In particular applications, the invention pertains to methods of forming dynamic random access memory (DRAM) arrays.
BACKGROUND OF THE INVENTION
A continuing goal in semiconductor processing is to reduce the amount of semiconductor wafer real estate consumed by integrated circuit devices. Exemplary integrated circuit devices are memory devices, such as, for example, DRAM devices. The DRAM devices are typically provided in arrays, with individual memory units comprising a transistor and a capacitor. Each individual DRAM unit of the array is provided with a unique address, which enables the individual units to be separately accessible relative to one another for reading and writing memory bits. It would be desirable to develop novel constructions of DRAM devices which reduce an amount of semiconductor real estate associated with the devices.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions having storage nodes. The capacitor constructions are defined to include a first set of capacitor constructions and a second set of capacitor constructions. A series of electrically conductive transistor gates are formed over the capacitor constructions and in electrical connection with the capacitor constructions. The transistor gates are defined to include a first set that is in electrical connection with the storage nodes of the first set of capacitor constructions, and a second set that is in electrical connection with the storage nodes of the second set of capacitor constructions. A first conductive line is formed over the transistor gates and in electrical connection with the first set of transistor gates, and a second conductive line is formed over the first conductive line and in electrical connection with the second set of transistor gates.
In another aspect, the invention encompasses an array of memory cells. The array includes a series of capacitor constructions, with the capacitor constructions being defined to include a first set and a second set. A conductive material is over the capacitor constructions, and in electrical connection with storage nodes of the capacitor constructions. A first conductive line is formed over the conductive material and in electrical connection with the first set of capacitor constructions through the conductive material. A second conductive line is over the first conductive line and in electrical connection with the second set of capacitor constructions through the conductive material. The second conductive line is electrically connected with the conductive material through conductive interconnects extending within openings in the first conductive line.


REFERENCES:
patent: 6423596 (2002-07-01), McKee

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