Process for improving mechanical strength of layers of low k...

Details Process for improving mechanical strength of layers of low k... Process for improving mechanical strength of layers of low k...

2002-05-03

2003-05-20

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S624000, C438S637000

Reexamination Certificate

active

06566244

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the formation of integrated circuit structures. More particularly, this invention relates to the formation of a structure comprising one or more layers of low k dielectric material having support structures therein to provide enhanced mechanical strength to the low k dielectric material.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U. K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (DUMIC) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H
2
O
2
to achieve a dielectric constant of ~2.9.
While such low k dielectric materials provide the needed reduction in capacitance by reduction in the dielectric constant (k) of the dielectric material, an undesired effect is reduction in mechanical strength as well. It has ben noted that, in general, the lower the dielectric constant of the dielectric material, the lower its strength becomes (as measured by Young's modulus of elasticity), probably because of the nature of the additives incorporated into the low k dielectric material and a reduction in the film density caused by micro-pores to achieve the desired reduction in dielectric constant.
This loss of mechanical strength was noted in Catabay and Hsia U.S. patent application Ser. No. 09,999,046, mailed to the USPTO by Express Mail on Oct. 26, 2001, assigned to the assignee of this patent application, and the subject matter of which is hereby incorporated herein by reference. Catabay and Hsia noted that when vias and/or trenches are formed in a layer or layers of such low k dielectric material and the resulting openings are filled with liner and filler materials, and when a polishing processing, such as a chemical mechanical polishing process (CMP), is used to remove excess filler and liner materials from the upper surface of the layer of low k dielectric material, the wafer pressure and the sheer strength of the polishing process could promote defects in the layer or layers of such weakened low k dielectric materials such as cracks and/or delamination. Sometimes even though the low k film made it through the CMP process without cracking, they noted that the low k film sometimes cracked during later processing such as packaging.
They proposed to add mechanical strength to such low k integrated circuit structures by reinforcing each layer of low k dielectric material, as it was constructed, This is shown in
FIG. 1
wherein a layer comprising metal lines
2
and low k dielectric material
4
is formed over an integrated circuit structure
1
and capped with a barrier layer
6
. A first layer
20
of low k dielectric material is then formed over barrier layer
6
.
Openings
26
a
-
26
d
are then formed in layer
20
of low k dielectric material (terminating at barrier layer
6
) and these openings are then filled with reinforcement material
21
having a higher Young's modulus of elasticity than that of layer
20
of low k dielectric material to thereby provide mechanical reinforcement to portions of low k dielectric layer
20
between vias
24
.
The formation of etch stop or barrier layer
22
over the resulting first reinforced layer is illustrative of the layer by layer formation of the reinforcement shown in FIG.
1
. The top surface of first reinforced layer
20
of low k dielectric material and reinforcement material
21
is covered with etch stop or barrier layer
22
which, as will be described below, then separates subsequently formed reinforced layers from the just described first reinforced layer comprising layer
20
of low k dielectric material and reinforcement material
21
.
Still referring to
FIG. 1
, a further layer of low k dielectric material
30
is shown formed over low k layer
20
and reinforced by high Young's modulus of elasticity reinforcement material
40
formed in openings
36
a
-
36
d
in low k dielectric layer
30
. Reinforcement material
40
also has a higher Young's modulus of elasticity than the low k dielectric material
30
shown being reinforced, i.e. similar to the previously described relationship between reinforcing material
21
and low k dielectric material
20
. It will be noted however, that openings
26
a
-
26
d
in low k dielectric layer
20
filled with reinforcing material
21
are aligned with, but physically separated from, openings
36
a
-
36
d
by the formation of barrier layer
22
after formation and reinforcement of low k dielectric layer
20
. Low k dielectric layer
40
is further shown with trench openings
34
formed therein in alignment and contiguous with vias
24
in layer
20
, as in a dual damascene construction.
While Catabay and Hsia thus reinforced the regions of low k dielectric material in their integrated circuit structure on a layer by layer basis throughout their integrated circuit structure, we have noted that often the damage seems to be concentrated in the bond pad regions of the integrated circuit structure. Such bond pad regions can tear off from the remainder of the integrated circuit structure, resulting in a bonding failure, probably because of the localized stresses created in these regions of the integrated circuit structure by wire bond pressure and vibration. This observation is of particular interest since portions of the integrated circuit not under the bonds pads have high speed logic circuitry where a higher k reinforcement material may not be needed and would be particularly undesirable if present.
It would, therefore, be desirable to optimize the reinforcement of mechanically weak low k dielectric material, both with regard to shape and position of the reinforcing material in the integrated circuit structure.
SUMMARY OF THE INVENTION
Selective reinforcement of certain regions of an integrated circuit containing low k dielectric material comprises reinforcing low k dielectric material selectively, in regions of the integrated circuit structure beneath the bonding pads, with reinforcing material having a higher Young's modulus of elasticity; and optionally extending such reinforcement material vertically and contiguously through multiple underlying layers of the integrated circuit structure.


REFERENCES:
patent: 5874367 (1999-02-01), Dobson
patent: 6309956 (2001-10-01), Chiang et al.
patent: 6313024 (2001-11-01), Cave et al.
patent: 6368952

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