Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-06-04

2003-05-13

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S230080

Reexamination Certificate

active

06563759

ABSTRACT:

BACKGROUND
The present invention relates to a semiconductor memory device which performs a read/write operation in a pipeline system in synchronism with a clock signal, and to a technology effective for application to, for example, a synchronous DRAM (Dynamic Random Access Memory) or a double data rate synchronous DRAM or the like.
With a rapid increase in operating frequency of a processor, there has also recently been a growing demand for the speeding up of a data transmission rate as well as the shortening of an access time as a demand for a DRAM. A synchronous DRAM operated in synchronism with a clock signal (hereinafter abbreviated as “clock”) has been developed with its demand. A DDR (Double Data Rate) type synchronous DRAM or the like for performing the input/output of data on the rising and falling edges of the clock has been proposed to achieve its further speeding up, which is becoming mainstream therefor.
The double data rate synchronous DRAM having such a configuration has been disclosed in 1999 ISSCC Digest of Technical Papers, p.412-p.413 (1999 IEEE Internal Solid-State Circuit Conference WP24.2 “A 2.5 V 333Mb/s/pin 1 Gb Double Date Rate SDRAM”, p.412-p.413).
Unexamined Patent Publication No. Hei 10-504129 (corresponding U.S. Pat. No. 5,544,124) discloses an optimizing circuit for a synchronous memory device having a programmable latency time. Unexamined Patent Publication No. Hei 10-162572 discloses a data transmission system capable of coping with various latency demands. Unexamined Paten Publication No. Hei 11-224486 (corresponding U.S. Pat. No. 6,151,270) discloses a synchronous memory device which controls activating
on-activating times of a column select signal according to a value corresponding to a CAS latency during a read operation. Unexamined Patent Publication No. Hei 11-66848 discloses a semiconductor memory device capable of operation with a sufficient margin of cycle time.
SUMMARY OF THE INVENTION
FIG. 29
shows a configuration of a double data rate synchronous DRAM discussed by the present inventors,
FIG. 30
shows a timing chart at its read operation, and
FIG. 31
shows a timing chart at its write operation, respectively. The following problems discussed by the present inventors and the analysis of causes of the problems are part of the present invention.
The semiconductor memory device shown in
FIG. 29
comprises a memory cell array
123
, an address buffer
101
which latches an address inputted from outside, an address register
103
which latches the address captured by the address buffer
101
, a row address decoder
109
which decodes a row address to thereby select a word line, a column address decoder
116
which decodes a column address to thereby select at least one bit line, a row address latch
104
which transmits a row address to the row address decoder
109
in response to the output of the address buffer
101
, a column address counter
111
which changes a column address thereinside, a column address latch
110
which transmits a column address to the column address counter
111
in response to the output of the address buffer
101
, a command decoder
102
which generates internal control signals in response to control signals supplied from outside, an output buffer
120
which outputs data read from the memory cell array
123
to the outside, an output clock generator
119
which controls timing for data outputted from the output buffer
120
, an input buffer
121
which receives data inputted from the outside, a read/write circuit
117
which transmits data read from the memory cell array
123
to the output buffer
120
or writing data inputted from the input buffer
121
into the memory cell array
123
, etc. One feature of the synchronous DRAM resides in that a CAS latency (corresponding to the number of clock cycles set from the capturing of a column address to the output of read data) can be set based on command codes (hereinafter called simply “commands”).
A read operation of data by the DRAM shown in FIG.
29
will be explained with reference to FIG.
30
.
FIG. 30
is a timing chart at the time that the number of clock cycles (tRCD) set from an ACTV command for providing instructions for the start of operation to a READ command or a WRITE command (called a column command where both commands are distinguished from each other) for providing read or write instructions is 2 cycles and a CAS latency is 2 cycles. As shown in
FIG. 30
, a row address is taken in from the address buffer
101
simultaneously with the time when an ACTV command is inputted. In response to the ACTV command, the row address is latched into the address register
103
according to ACLK outputted from a command decoder
102
. Further, the row address is latched into the row address latch
104
according to a clock RCLK outputted from the command decoder
102
in response to the ACTV command. Afterwards, the rod decoder
109
decodes the row address signal to thereby select a word line corresponding to the value of the row address. When the corresponding word line is selected, data is outputted from a memory cell connected to the selected word line to at least one bit line. When the data is fully outputted to the bit line, a sense amplifier is started up so that the potential on the bit line is amplified.
A READ command is inputted after the elapse of two cycles since the entry of the ACTV command. Simultaneously with it, a column address is taken in from the address buffer
101
. In response to the READ command, the column address is latched into the address register
103
according to a clock ACLK outputted from the command decoder
102
. Further, the column address is latched into the column address latch
110
according to a clock YCLK
1
outputted from the command decoder
102
in response to the READ command. Afterwards, the column address signal passes through the column address counter
111
and is decoded by the column decoder
116
to thereby select at least one bit line corresponding to the value of the column address. At this time, a bit-line selectable condition is that the potential on at least one bit line has fully been amplified. After the selection of the bit line, data on the bit line passes through the read circuit
117
and is outputted to the outside through the output buffer
120
. At this time, the timing provided to output read data to the outside through the output buffer
120
is determined according to QCLK
1
generated from the output clock generator
119
. In the double data rate synchronous DRAM, 2n-bit data equivalent to twice the number of output bits (n) are read from the read circuit
117
to the output buffer
120
, and the data are outputted by n bits in synchronism with the rising and falling edges of the clock. Incidentally, a column decoder input and a column select signal are shown in
FIG. 30
two by two because continuous addresses are generated from the column address counter
111
in a burst mode or the like and the read operation is carried out based on the same addresses.
FIG. 31
shows a timing chart at a data writing of the DRAM shown in
FIG. 29
where tRCD is 2 cycles and a CAS latency is 1 cycle. As shown in
FIG. 31
, a row address is taken in simultaneously with the entry of an ACTV command upon writing. The row address is decoded by the row decoder
109
to select a word line. Data stored in a memory cell is outputted to at least one bit line. When the bit line is fully set up, a sense amplifier is started up to amplify the potential on the bit line.
A WRITE command is inputted after the elapse of 2 cycles since the entry of the ACTV command. Simultaneously with the entry of the WRITE command, a column address is taken in. Afterwards, the column address is decoded in a manner similar to the reading to thereby select at least one bit line. Write data is captured from outside in 1 cycle=(CAS latency−1) since the entry of the WRITE command. In the double data rate synchronous DRAM at this time, n-bit write data are respectively taken in by the input buffer
121
on both the rising an

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