Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-08-24
2003-07-22
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100, C365S230030, C365S227000
Reexamination Certificate
active
06597615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to refresh control in a semiconductor memory device.
2. Description of the Related Art
Commonly used semiconductor memory devices include DRAM and SRAM. It is common knowledge that while DRAM offers higher capacity at lower price than SRAM, it requires refresh operations. SRAM, on the other hand, while easier to use due to the lack of a need for refresh operations, is more expensive and has lower capacity than DRAM.
Virtual SRAM (known as VSRAM or PSRAM) is a semiconductor memory device that offers those advantages of both DRAM and SRAM. Virtual SRAM has a memory cell array composed of dynamic memory cells identical to those in DRAM, and also houses a refresh controller allowing refresh operations to be performed internally. Thus, external devices connected to virtual SRAM (such as a CPU) can access (i.e., read or write data) virtual SRAM without being aware of refresh operations. This feature of virtual SRAM is known as “refresh transparency.”
Certain types of virtual SRAM can assume a plurality of operating modes, such as a normal operating mode and a power saving mode. The issue of how internal refresh operations should be performed in virtual SRAM in each of these operating modes has not been given adequate consideration. This problem is not limited to so-called virtual SRAM, and is a problem common to all types of dynamic semiconductor memory devices that have an internal refresh timer and refresh controller.
SUMMARY OF THE INVENTION
An object of the present invention is to enable refresh operations to be carried out optimally in each of a plurality of available operating modes of a semiconductor memory device.
In order attain at least part of the above and related objects of the present invention, there is provided a semiconductor memory device having a plurality of operating modes. The semiconductor memory device comprises a memory cell array having dynamic memory cells, a refresh controller, an operation mode input terminal, and an external timing input terminal. The refresh memory controller has a refresh timer for generating a refresh timing signal used to determine timing for performing refresh operations on the memory cell array. The refresh controller performs refresh operations on the memory cell array in response at least to the refresh timing signal. The operating mode input terminal is configured to receive from an external device an operating mode signal specifying one of the plurality of operating modes of the semiconductor memory device. The external timing input terminal is configured to receive from the external device an external timing signal that is to be used together with the refresh timing signal when the refresh controller determines the timing for performing the refresh operations.
The refresh controller performs internal refresh operations in two refresh modes. In an event that the operating mode signal specifies a first operating mode, the refresh controller performs an internal refresh operation according to a first refresh mode wherein a refresh operation on the memory cell array is initiated under timing determined by the external timing signal after the refresh timing signal has been generated. In an event that the operating mode signal specifies a second operating mode, on the other hand, the refresh controller performs an internal refresh operation according to a second refresh mode wherein a refresh operation on the memory cell array is initiated in response to generation of the refresh timing signal, regardless of the external timing signal.
In first operating mode, an internal refresh operation is initiated under timing determined by an external timing signal, thereby facilitating arbitration of access operations by external devices and internal refresh operations by the refresh controller. In second operating mode, an internal refresh operation is initiated in response to generation of a refresh timing signal, regardless of an external timing signal, thereby enabling internal refresh operations even in the absence of external timing signal input. Thus, refresh operations in this semiconductor memory device are performed in suitable ways for each of the plurality of operating modes.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with the accompanying drawings.
REFERENCES:
patent: 5777942 (1998-07-01), Dosaka et al.
patent: 6028804 (2000-02-01), Leung
patent: A 11-297067 (1999-10-01), None
Hur Jung H.
Oliff & Berridg,e PLC
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