Semiconductor device having MOS transistor for coupling two...

Details Semiconductor device having MOS transistor for coupling two... Semiconductor device having MOS transistor for coupling two...

2000-12-21

2003-07-22

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S297000, C257S298000

Reexamination Certificate

active

06597040

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having first and second signal lines and a MOS transistor for coupling the lines.
2. Description of the Background Art
System LSIs have been developed which are mounted with DRAM core cells and logic circuits. In order to improve a data transfer rate, input and output of hundreds of bits of data at a time is enabled between a DRAM core cell and a logic circuit. In addition, an input terminal for a one-bit write mask signal is provided for every plurality of bits, and controlling of the write mask signal enables rewriting of data of memory cells of the corresponding plurality of bits to be inhibited.
FIG. 12
is a block diagram showing an entire structure of such a DRAM core cell
30
. In
FIG. 12
, the DRAM core cell
30
includes a row/column address buffer+clock generation circuit
31
, a row/column decoder circuit
32
, a memory mat
33
and a data input/output circuit
34
. In the DRAM core cell
30
, 8 k bits of data DQ
1
-8 k (k: integer not less than 1) can be input and output at a time and an input terminal for a one-bit write mask signal WM is provided for every 8 bits of data.
The row/column address buffer+clock generation circuit
31
generates row address signals RA
0
-m, column address signals CA
0
-CAm, a read clock signal CLKR and a write clock signal CLKW in accordance with external address signals A
0
-Am (m: integer not less than 0) and external control signals /RAS, /CAS, /WE to control the entire DRAM core cell
30
.
The memory mat
33
includes a plurality of sense amplifier bands SA
1
-SA
3
and memory cell arrays MA
1
and MA
2
arranged between the bands. The memory cell arrays MA
1
and MA
2
each include a plurality of memory cells for storing one bit of data. The plurality of memory cells are grouped by a predetermined number, 8 k bits. Each memory group is arranged at a predetermined address deter-mined by a row address and a column address.
The row/column decoder circuit
32
designates addresses of the memory cell arrays MA
1
and MA
2
in accordance with the row address signals RA
0
-RAm and the column address signals CA
0
-CAm applied from the row/column address buffer+clock generation circuit
31
. In the sense amplifier bands SA
1
and SA
2
, a sense amplifier+input/output control circuit group which will be described later is provided. The sense amplifier+input/output control circuit group connects the number 8 k of memory cells at the addresses designated by the row/column decoder circuit
32
to the data input/output circuit
34
. The data input/output circuit
34
includes a write driver+read amplifier band
35
and an input/output buffer group
36
. In the write driver+read amplifier band
35
, a write driver group and a read amplifier group are provided.
The read amplifier group operates in synchronization with the read clock signal CLKR to apply read data Q
1
-Q
8
k
from the number 8 k of selected memory cells to the input/output buffer group
36
. The input/output buffer group
36
externally outputs the read data Q
1
-Q
8
k
from the read amplifier group in response to an external control signal /OE. The write driver group operates in synchronization with the write clock signal CLKW to write external write data D
1
-D
8
k
into the number 8 k of selected memory cells. Of the number 8 k of memory cells, no data will be written into the memory cells designated by write mask signals WM
1
-WMk.
Each of the memory cell arrays MA
1
and MA
2
includes the number 8 k of memory blocks MB provided corresponding to the data DQ
1
-DQ
8
k
. Each memory block MB, as shown in
FIG. 13
, includes a plurality of memory cells MC arranged in a plurality of rows and columns, a plurality of word lines WL provided corresponding to the plurality of rows, and a plurality of bit line pairs BL, /BL provided corresponding to the plurality of columns. The memory cell MC is a known MC including an N channel MOS transistor Q for access and a capacitor C for information storage.
When a word line WL corresponding to the row address signal RA
0
-RAm is brought to a logical high or a “H” level as a selection level by the row/column decoder circuit
32
, an N channel MOS transistor Q of a memory cell MC at a row corresponding to the word line WL is rendered conductive to enable data writing/reading of the memory cell MC. In writing operation, after activating a memory cell MC by forcing one word line WL to a “H” level as the selection level, one bit line of a bit line pair BL, /BL is forced to a “H” level and the other to a logical low or a “L” level in accordance with the write data D. As a result, a potential of the bit line is written into a capacitor C of a desired memory cell MC. In reading operation, after equalizing potentials of the bit line pair BL, /BL to VBL (=VCC/2), the memory cell MC is activated by forcing one word line WL to a “H” level as the selection level. As a result, a minute potential difference is generated between BL and /BL of each bit line pair according to storage data of the memory cell MC. By amplifying a minute potential difference between bit lines of each pair to a power supply voltage Vdds and then detecting a potential difference between bit lines of one bit line pair, data in a desired memory cell MC can be read. The number 8 k of memory blocks MB are arrayed in a direction in which the word lines extend and the word lines WL are shared by the number 8 k of memory blocks MB.
FIG. 14
is a circuit block diagram showing a structure of a part related to writing/reading of the data DQ
1
. In
FIG. 14
, provided are a write driver
37
and a write data line pair GIOW, /GIOW for the writing of the data D
1
, and a read amplifier
38
and a read data line pair GIOR, /GIOR for the reading of the data Q
1
.
The write driver
37
is arranged in the write driver+read amplifier band
35
shown in
FIG. 12
for forcing one of the write data lines GIOW and /GIOW to a “H” level and the other to a “L” level in accordance with the write data D
1
in writing operation. The read amplifier
38
is arranged in the write driver+read amplifier band
35
for detecting a potential difference between a read data line pair GIOR, /GIOR to generate the read data Q
1
and externally output the same through the output buffer in reading operation.
The write data line pair GIOW, /GIOW is arranged to cross the memory arrays MA
1
and MA
2
and the sense amplifier bands SA
1
-SA
3
shown in FIG.
12
and has its one end connected to the write driver
37
. The read data line pair GIOR, /GIOR is arranged to cross the memory arrays MA
1
and MA
2
and the sense amplifier bands SA
1
-SA
3
and has its one end connected to the read amplifier
38
.
A sense amplifier+input/output control circuit
40
is provided commonly for one pair of bit lines BL
1
and /BL
1
included in a memory block MB of the memory cell array MA
1
and one pair of bit lines BL
2
and /BL
2
included in a memory block MB of the memory cell array MA
2
. The sense amplifier+input/output control circuit
40
is provided, for example, for each odd-numbered bit line pair BL, /BL of the memory cell arrays MA
1
and MA
2
and arranged at the sense amplifier band SA
2
. Sense amplifier+input/output control circuits each for each even-numbered bit line pair BL, /BL of the memory cell arrays MA
1
and MA
2
are arranged in the sense amplifier bands SA
1
and SA
3
, respectively.
The sense amplifier+input/output control circuit
40
includes N channel MOS transistors
41
to
44
, equalizers
45
and
46
, a sense amplifier
47
, a write gate
50
and a read gate
60
. The N channel MOS transistors
41
and
42
are connected between the bit lines BL
1
and /BL
1
of the memory cell array MA
1
and nodes N
1
and N
2
, respectively, and each have a gate receiving a signal SHR
1
. The N channel MOS transistors
43
and
44
are connected between the bit lines BL
2
and /BL
2
of the

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