Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-29
2003-01-07
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06505332
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method and an apparatus for wiring layout in designing circuit devices such as semiconductor integrated circuits, and more particularly to a method and an apparatus for calculating a basic delay time using different wiring resistance values depending on the existence of and/or the distance to an adjacent wire at respective positions of respective wires and generating a logic cell library which stores the basic delay time.
2. Description of the Related Art
With higher integration in semiconductor integrated circuits, longer wiring is integrated with smaller interval in a limited area within a circuit, and the. sectional shape of the circuit becomes finer and more complicated. As a result, wiring in the semiconductor integrated circuit has a larger resistance value and a larger capacitance value. Increases in the wiring resistance value and wiring capacitance value cause a longer wiring delay time accordingly since the wiring delay time is derived by multiplying the wiring resistance value by the wiring capacitance value. Such a longer wiring delay time tends to reduce the propagation speed of signals within the integrated circuit.
To solve the aforementioned problem, the present inventor has already proposed a new logic cell library generating apparatus and a wiring layout apparatus in JP-A-11067916.
FIGS. 1 and 2
are diagrams showing the logic cell library generating apparatus and the wiring layout apparatus disclosed in JP-A-11067916, respectively.
The logic cell library generating apparatus shown in
FIG. 1
comprises sectional shape file
101
for accumulating the sectional shape of wiring, material data file
102
for accumulating property constants of materials of the wiring or interlayer dielectrics, and arrangement information file
103
for storing information on the arrangement of the wiring. Data is inputted from these files
101
to
103
to device simulator
105
for deriving capacitance values and resistance values at respective positions in the wiring. Device simulator
105
outputs the capacitance values and resistance values which are to be stored in library
106
. Mask layout pattern file
107
, first net list file
109
and test standard file
111
store mask layout patterns, net lists and test standards, respectively. In this logic cell library generating apparatus, layout verification tool
108
verifies wiring layout using as its input the stored contents in library
106
and mask layout pattern file
107
to derive input loads and output driving capability. Layout verification tool
108
outputs the input load data and output driving capability data and these data are stored in storage device
110
. Circuit simulator
112
refers to the output from storage device
110
, the contents of first net list file
109
and the contents of test standard file
111
to perform a circuit simulation. First delay calculator
113
calculates a basic delay time based on the output from circuit simulator
112
. The basic delay time thus calculated is stored in logic cell library
114
.
The conventional wiring layout apparatus shown in
FIG. 2
comprises router
133
for performing wiring layout using as its input the basic delay time stored in logic cell library
114
produced with the logic cell library generating apparatus shown in
FIG. 1
, and using the net list information stored in second net list file
132
. On the output side of router
133
, second delay calculator
135
is provided for calculating a delay time using as its input three-dimensional arrangement information on the wiring and the absence or presence of an adjacent wire outputted from router
133
, and wiring capacitance values and wiring resistance values according to the three-dimensional wiring arrangement stored in library
134
. Comparator
135
compares the delay time outputted from second delay calculator
135
with a reference value, and if the outputted delay time does not match the reference value, causes router
133
to start processing.
It should be noted that the adjacent wire in the foregoing refers to a wire (or wires) adjacent to a wire on one side or both sides thereof at respective positions in each wire. However, when an interval of certain distance (for example, 1000 nm) or more exists between a wire and its adjacent wire, the wire is considered as an isolated wire which has no adjacent wire, even if the two wires are arranged adjacently.
The presence of an adjacent wire significantly affects a wiring resistance value. The wiring resistance value has the largest value when adjacent wires exist respectively on both sides of a wire, and is the second larges value when an adjacent wire exists on one side of a wire. An isolated wire with no adjacent wires on either of the sides has the smallest wiring resistance value. Here, the adjacent wire of an objective wire is defined as a wire that exists within a predetermined distance (for example, 1000 nm) from the objective wire.
The invention disclosed in JP-A-11067916 generates, with the aforementioned configuration, logic cell library
114
for storing the capacitance values and resistance values at respective positions based on the sectional shape of multi-layered wiring, the property constants of materials of the wiring and interlayer dielectrics and the wiring arrangement information, and performs wiring layout using logic cell library
114
.
However, a wire width and a wiring interval are smaller as wiring is finer, with the result that a completed wire width is significantly affected by the amount of a reactive product from a photoresist and etching gas which is attached to side walls of the wire at etching in a fabricating process of a semiconductor integrated circuit. A wider wiring interval causes a larger amount of the reactive product to be attached to the wire side walls, thereby making the wire width larger than the width defined by photolithography. On the other hand, when the wiring interval is smaller, the wire width is substantially the same as the width defined by the photolithography due to a smaller amount of the reactive product.
FIG. 3
shows dependence of a completed wire width obtained after etching of an aluminum wiring layer on a distance from an adjacent wire. In
FIG. 3
, a vertical axis represents the wire width after etching (in &mgr;m) while a horizontal axis represents a spacing from an adjacent wire (in &mgr;m). Black circles represent the case of adjacent wires existing on both sides, while white circles represent the case of an adjacent wire on one side at a distance of 1 &mgr;m or less. A design wire width is constant (300 nm). It can be seen from
FIG. 3
that a wider wiring interval causes a wider completed wire width, and a difference occurs at an interval of approximately 300 nm in the completed wire width between the case of adjacent wires existing on both sides and the case of an adjacent wire on one side at a distance of 1 &mgr;m or less, and a near state of saturation is reached at a spacing of 1000 nm.
Since wiring has a certain length, it has a distributed constant value. The distributed constant value leads to delay during propagation of signals in the wiring, resulting in a difference in the arrival time of the signals, which is referred to as wiring delay. In a semiconductor integrated circuit or the like, a difference occurs between the time taken for a signal to reach a cell disposed near a cell and the time taken for a signal to reach a cell disposed at the end of wiring. The wiring delay is not particularly serious at a wire width of 0.5 &mgr;m or more.
The inherent delay of a cell is a value inherent in each cell and refers to a value of delay from the rise of input pins to the fall of output pins under non-load conditions where no load is applied to a logical gate. The wiring capacitance refers to a capacitance generated from interconnection of logic cells through a wire.
When portions with no adjacent wire are increased, the wire width and wiring resistance value are reduced according
Hayes & Soloway PC
Lin Sun James
NEC Corporation
Smith Matthew
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