Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
1999-10-22
2003-01-21
Wong, Peter (Department: 2781)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S052000, C710S056000
Reexamination Certificate
active
06510475
ABSTRACT:
TECHNICAL FIELD
The present invention relates to data fetching, and more particularly, relates to a data fetch control mechanism and method of fetching optimized data from a memory subsystem on one side of a host bridge such as a PCI—PCI bridge for bus devices such as Peripheral Component Interconnect (PCI) devices on the other side of the host bridge.
BACKGROUND
Historically, computer systems have utilized one or more buses as an interconnect transportation mechanism to transfer data between different internal components, such as one or more processors, memory subsystems and input/output (I/O) devices including, for example, keyboards, input mouses, disk controllers, serial and parallel ports to printers, scanners, and display devices. For computer systems using processors such as the 8088, 8086, 80186, i386™ and 486™ microprocessors designed and manufactured by Intel Corporation, such buses have typically been designed as either an Industry Standard Architecture (ISA) bus or an Expanded Industry Standard Architecture (EISA) bus. The ISA bus is a sixteen (16) bit data bus while the EISA bus is thirty-two (32) bits wide. Each of these buses functions at a frequency of eight (8) megahertz. However, the data transfer rates provided by these bus widths and operational frequencies have been limited.
For recent computer systems, such as servers, workstations or personal computers (PCs) using a “Pentium®” family of microprocessors (manufactured by Intel Corporation), for example, such buses may be Peripheral Component Interconnect (PCI) buses. The PCI buses are high performance 32 or 64 bit synchronous buses with automatic configurability and multiplexed address, control and data lines as described in the latest version of “PCI Local Bus Specification, Revision 2.2” set forth by the PCI Special Interest Group (SIG) on Dec. 18, 1998. Currently, the PCI architecture provides the most common method used to extend computer systems for add-on arrangements (e.g., expansion cards) with new video, networking, or disk memory storage capabilities.
When PCI buses are used as an interconnect transportation mechanism in a host system (e.g., server, workstation or PC), data transfer between a processor, a memory subsystem and I/O devices may be executed at high speed. Bridges may be provided to interface and buffer transfers of data between the processor, the memory subsystem, the I/O devices and the PCI buses. Examples of such bridges may include PCI-PCI bridges as described in detail in the “
PCI
-
PCI Bridge Architecture Specification, Revision
1.1” set forth by the PCI Special Interest Group (SIG) on Apr. 5, 1995. However, the performance of such a host system may be burdened by a significant amount of time required to process read requests from PCI devices (e.g., I/O devices that conform to the PCI Local Bus Specification for operation) to access memory locations of the memory subsystem, via the PCI buses, during data memory read operations. Existing data fetching schemes for PCI devices, however, fail to optimize the PCI bus operation. Typically, data fetched from the memory subsystem are at a standard size, and may not be optimized at various fetch sizes for PCI devices behind or on one side of a host bridge such as a PCI-PCI bridge based upon a particular request. As a result, the memory read operations may not be maximized, and the wait time between memory read operations may be unnecessarily lengthened.
Accordingly, there is a need for an efficient data fetching control mechanism which fetches optimized data from a memory subsystem on one side of a host bridge such as PCI-PCI bridge for PCI devices on the other side of the host bridge in accordance with characteristics of a particular request, such as a command type, a data width, a clock frequency and a cache line size.
SUMMARY
Accordingly, various embodiments of the present invention are directed to a data fetching control mechanism and a method for determining a fetch size to fetch data from a memory subsystem of a computer system. Such a mechanism may comprise input logics coupled to receive variables of a read command, a bus frequency, and a bus data width from a bus device; and an index table which generates fetch values indicating fetch sizes of data to be fetched from a memory subsystem on one side of a host chipset, via a primary bus, for the bus device on an opposite side of the host chipset, via a secondary bus.
REFERENCES:
patent: 5768548 (1998-06-01), Young et al.
patent: 5778197 (1998-07-01), Dunham
patent: 5838995 (1998-11-01), Chen et al.
patent: 5872998 (1999-02-01), Chee
patent: 5884027 (1999-03-01), Garbus et al.
Antonelli Terry Stout & Kraus LLP
Intel Corporation
Vo Tim
Wong Peter
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