Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-14
2003-07-15
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S343000, C257S547000, C257S548000, C257S557000
Reexamination Certificate
active
06593629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a high-withstand-voltage npn transistor used to drive an ABS (Antilock Brake System), an air bag, and a display of an automobile, drive a fluorescent display panel, and control a motor.
2. Description of the Background Art
FIG. 16
is a sectional view of a conventional npn transistor. An n
+
-type buried layer
102
is located on a p
−
-type substrate
101
and an n
−
-type epitaxial layer
104
is formed so as to cover the n
+
-type buried layer
102
and the p
−
-type substrate
101
. The substrate denotes a semiconductor substrate in the present invention. A p
+
-type diffused layer
116
formed so as to reach the p
−
-type substrate
101
by diffusion from the surface of the n
−
-type epitaxial layer
104
functions for element separation and moreover, a LOCOS oxide film
106
is formed on the surface of the layer
116
. Moreover, the following are formed on the layer
116
: an oxide film formed by thermally oxidizing the surface of the n
−
-type epitaxial layer.
104
up to a thickness of tens of nanometers to adjust an injection depth (not illustrated), a p
+
-type diffused layer
118
formed by injection from the surface of the oxide film, and an n
+
-type diffused layer
109
formed by injection from the surface of the p
+
-type diffused layer
118
. Moreover, a p
+
-type diffused layer
110
formed by injection from the surface of the p
+
-type diffused layer
116
is formed as a base contact and a oxide film layer
111
is formed on outermost surfaces of the LOCOS oxide film
106
, n
+
-type diffused layer
109
, and p
+
-type diffused layer
110
so as to cover them. Furthermore, a wiring
112
a,
112
b,
112
c
formed in a contact hole formed to be reached to the n
+
-type diffused layer
109
and p
+
-type diffused layer
110
from the surface of the oxide-film layer
111
by dry etching so as to bury the contact hole.
Then, a method for fabricating the structure shown in
FIG. 16
is described below by referring to
FIGS. 17 and 18
. First, the surface of the p
−
-type substrate
101
is oxidized and photoengraving is performed to remove an oxide film. Then, the n
+
-type buried layer
102
is formed by injecting antimony into the p
−
-type substrate
101
, and heating the substrate
101
to 1,240° C. and thereby driving it to remove the oxide film from the surface of the p
−
-type substrate
101
. Then, as shown in
FIG. 17
, the n
−
-type epitaxial layer
104
is formed on the outermost surface of the p
−
-type substrate
101
on which the n
+
-type buried layer
102
is formed.
Then, the surface of the n
−
-type epitaxial layer
104
is oxidized up to hundreds of nanometers to perform photoengraving, inject boron, and perform driving at 1,180° C., and form the p
+
-type diffused layer
116
used for element separation (refer to FIGS.
17
and
18
). Then, oxide films are removed from outermost surfaces of the p
+
-type diffused layer
116
and n
−
-type epitaxial layer
104
to form an oxide film having a thickness of tens of nanometers. Then, a nitride film is deposited to perform photoengraving and then, the nitride film is removed to form a LOCOS oxide film. Then, the oxide film at a thickness of tens of nanometers and the LOCOS oxide film
106
are removed up to a thickness of tens of nanometers to form an oxide film
117
up to a thickness of 10 to 50 nm. Then, resist is applied to perform patterning and boron is injected to perform driving and form a p
+
-type diffused layer
118
serving as the base region of npn transistor. Next, photoengraving is performed in order to form a n
+
-type diffused layer
109
serving as the emitter region of the npn transistor, and arsenide is injected and driving is performed at 900° C. in a nitride atmosphere. Then, as shown in
FIG. 18
, to improve the ohmic contact of the base contact of the npn transistor, the p
+
-type diffused layer
110
is formed by injecting BF
2
.
Then, the oxide-film layer
111
is deposited and photoengraving is performed to form a contact hole on the oxide-film layer
111
so as to contact each diffused-layer region and photoengraving is performed by sputtering aluminum. Then, as shown in
FIG. 16
, aluminum is removed to form an aluminum electrode contacting each diffused-layer region.
By using the above structure, it is possible to obtain an npn transistor having a high withstand voltage and a high operation speed.
In the case of the npn transistor having the above configuration, however, the base region is common to the substrate. Therefore, when driving a transistor for emitter grounding, it is necessary to apply to an emitter a potential lower than that of the base region whose potential is common to a substrate having a zero potential. Therefore, it is necessary to constitute a negative-voltage source in an IC (Integrated Circuit). Thus, a circuit becomes complex, the number of fabrication steps increases, and the cost increases. Therefore, it has been desired to develop an npn transistor in which a potential can be more easily set to each terminal.
SUMMARY OF THE INVENTION
It is a main object of the present invention to provide an npn transistor in which it is unnecessary to constitute a negative-voltage source in an IC for emitter grounding and it is possible to easily set the potential of each terminal. It is another object of the present invention to provide an npn transistor achieving the above main object and moreover, superior in characteristics such as a withstand-voltage performance and a current amplification factor.
A semiconductor device of the present invention is provided with an n-type buried layer formed on a p-type semiconductor substrate, a p-type buried layer formed on the n-type buried layer, an n-type epitaxial layer formed on a p-type semiconductor substrate, the n-type buried layer, and the p-type buried layer so as to cover them, an n-type emitter region, a p-type base region encircling the n-type emitter region by contacting it from the inside, and a n-type collector region which are respectively located at the surface of the n-type epitaxial layer, and a p-type outer-periphery layer located at the surface of the n-type epitaxial layer, encircling the n-type emitter region, the p-type base region, and the n-type collector region from the circumference when viewed from above. Moreover, in the case of this semiconductor device, the n-type epitaxial layer includes an n-type encirclement layer contacting the outer periphery of the p-type outer-periphery layer and the p-type base region and p-type buried layer as well as the p-type outer-periphery layer and p-type buried layer are respectively continued to divide the n-type epitaxial layer and separate the n-type collector region from the p-type semiconductor substrate, and the n-type buried layer and the n-type encirclement layer are continued to separate the continued p-type buried layer, p-type base region, and p-type outer-periphery layer from the p-type semiconductor substrate.
According to the above configuration, terminal regions of the emitter, base, and collector regions are separated from the p-type substrate. That is, it is possible to lift the npn transistor from the p-type substrate. Therefore, it is possible to arbitrarily set the potential of each terminal to zero potential or higher correspondingly to a wiring pattern. For example, when using a wiring pattern for emitter grounding, it is possible to apply an arbitrary positive potential to a base or collector terminal by connecting an emitter terminal to the p-type substrate to make the potential common to that of the substrate. Therefore, it is unnecessary to set a negative-voltage source required to drive the emitter of a conventional npn transistor in which a base region is electrically connected with a substrate in an IC in emitter grounding. That is,
Flynn Nathan J.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Sefer Ahmed N.
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