Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,...
Reexamination Certificate
2001-04-30
2003-07-01
Ta, Tho D. (Department: 2833)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
C439S060000, C439S924100, C439S059000, C439S065000, C361S760000
Reexamination Certificate
active
06585525
ABSTRACT:
RELATED APPLICATIONS
This application claims priority from Korean Application No. 00-23105, filed Apr. 29, 2000 and Korean Application No. 00-47147, filed Aug. 16, 2000.
FIELD OF THE INVENTION
The present invention relates to memory modules in general, and more particularly, to the expansion of memory modules.
BACKGROUND OF THE INVENTION
It is known to provide communications between devices on a system board via a system bus including, for example, a control bus, an address bus, and a data bus. The busses may be shared by devices on the system board such as a microcontroller, a memory module, and an input/output device. The memory module may be controlled by a memory controller to use an internal serial bus to provide high speed operation.
FIG. 1
illustrates a system board
10
having a conventional serial bus
9
thereon. The system board
10
can include a plurality of memory modules
12
,
14
and
16
, in respective sockets
13
,
15
, and
17
. The memory modules
12
,
14
and
16
can be connected to a memory controller
11
via the serial bus
9
. Signals from the memory controller
11
may be provided to the memory module
12
via connector pins on the memory module
12
when the memory module
12
is inserted into the socket
13
. The signals provided to the memory module
12
can be used to address memory devices on the memory module
12
. The signals can also be conducted across the memory module
12
to other connector pins thereon so that the signals can also be provided to the memory modules
14
and
16
via the serial bus
9
. For example, a signal can be conducted from the memory controller
11
onto the memory module
12
, across the memory module
12
, off the memory module
12
to the memory module
14
, across the memory module
14
, off the memory module
14
to the memory module
16
, across the memory module
16
, and off the memory module
16
to the termination resistor Rterm which terminates the serial bus
9
.
It is known to increase bandwidth by increasing the number of signal lines provided to the memory modules. Accordingly, as the number of signal lines increases, so may the number of connector pins on the memory modules. Therefore, the memory module may also increase in size to accommodate the increased number of signals. As the size of the memory module increases, the sockets may also become larger which may increase the size of the system board
10
. Increasing the size of the sockets and the system board
10
may also increase the length of the transmission lines used to carry the signals from one socket to another. To compensate for this, buffers or repeaters (not shown) may be added to the signal lines to reduce the deterioration of the signals. Adding such devices may increase the cost of the system.
SUMMARY OF THE INVENTION
Embodiments according to the present invention can provide memory modules having a plurality of connector pins adjacent to a first edge of the memory module that are configured to conduct a plurality of first signals to or from the memory module via the first edge and a plurality of first conductors adjacent to a second edge of the memory module that are configured to conduct a plurality of second signals to another memory module that is substantially coplanar with the memory module via the second edge.
In some embodiments according to the present invention, the first and second edges are oriented in different directions. In other embodiments, the memory modules can further include a plurality of second conductors that are adjacent to a third edge of the memory module which is opposite the second edge and are electrically connected to selected ones the plurality of connector pins.
In other embodiments, the plurality of second conductors are electrically connected to the plurality of first conductors. In other embodiments according to the present invention, the plurality of connector pins are arranged in a row. In still other embodiments according to the present invention, the plurality of first conductors are arranged in columns wherein adjacent ones of the columns are offset relative to one another in the column direction.
In some embodiments according to the present invention, the plurality of first conductors and the plurality of second conductors are on a first side of the memory module and the memory module further includes a plurality of conductive lines that are on a second side of the memory module, opposite the first side, which electrically connect the plurality of first conductors and the plurality of third conductors.
Pursuant to further embodiments according to the present invention, a memory module socket can be configured to be mounted on a system board and configured for insertion of first and second memory modules therein. The memory module socket can include a connector pin interface that is configured to electrically connect a plurality of first conductive lines on the system board to a plurality of first conductors located at a first edge of the first memory module when the first memory module is inserted in the memory module socket and a first conductor interface that is configured to electrically connect to a plurality of second conductors on the first memory module to the second memory module when the first memory module is inserted in the memory module socket.
In some embodiments according to the present invention, the first conductor interface and the connector pin interface are oriented in different directions. In other embodiments, the memory module socket includes an intermediate portion of the memory module socket that defines first and second slots of the memory module socket. The first conductor interface is configured to electrically conduct signals from a first memory module in the first slot to a second memory module in the second slot via the intermediate portion without using the connector interface.
Pursuant to further embodiments, memory modules according to the present invention can include a circuit board, a plurality of memory devices on the circuit board, a plurality of pins that are electrically connected to the plurality of memory devices in a predetermined region of the circuit board, and a plurality of connector pins that are electrically connected to the plurality of memory devices on both sides of the region in which the memory chips are located on the circuit board.
REFERENCES:
patent: 4685031 (1987-08-01), Fife et al.
patent: 5189598 (1993-02-01), Bolan et al.
patent: 5270964 (1993-12-01), Bechtolsheim et al.
patent: 6205031 (2001-03-01), Herzog et al.
patent: 6273759 (2001-08-01), Perino et al.
patent: 6347039 (2002-02-01), Lee
patent: 55045124 (1980-03-01), None
patent: 6061289 (1994-02-01), None
patent: 11088380 (1999-03-01), None
patent: P2000-0018572 (2000-04-01), None
Notice to Submit Response, Korean Application No. 10-2000-0047147, Jun. 18, 2002.
Jung Tae-sung
Song Won-ki
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Ta Tho D.
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