Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-03
2003-09-09
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S349000, C257S350000, C257S351000, C257S408000, C438S149000, C438S479000, C438S517000
Reexamination Certificate
active
06617644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a circuit composed of a thin film transistor on a substrate that has an insulating surface, and to a method of manufacturing the same. For instance, the invention relates to the construction of an electro-optical device, exemplified by a liquid crystal display device, and an electronic equipment provided with the electro-optical device. Incidentally, the semiconductor device in the present specification designates devices in general which function by utilizing semiconductor characteristic. The electro optical device and electronic equipment provided with the electro optical device mentioned above therefore fall into category of the semiconductor device.
2. Description of the Related Art
Development in application of thin film transistors (hereinafter referred to as TFT) to active matrix liquid crystal display devices has been actively proceeded, because TFT allows the use of a transparent grass substrate in fabrication. The TFT having as its active layer a semiconductor film with a crystal structure (hereinafter referred to as crystalline TFT) provides high mobility, making it possible to integrate function circuits on a single same substrate and thus realize image display of high definition.
In the present specification, the semiconductor film with a crystalline structure, mentioned above, includes a single crystalline semiconductor, a polycrystalline semiconductor and a microcrystalline semiconductor, and further includes semiconductors disclosed in Japanese Patent Application Laid-Open Nos. Hei 7-130652, Hei 8-78329, Hei 10-135468, and Hei 10-135469.
Upon construction of an active matrix liquid crystal display device, a pixel matrix circuit alone requires 1 to 2 million crystalline TFTs, and even more crystalline TFTs in total need to be contained if function circuits to be disposed at the periphery are added. Also, reliability of each of those crystalline TFTs has to be secured in order to operate stably the liquid crystal display device.
It can be said that characteristic of field effect transistors, such as TFTs, has three distinguishable domains: a linear domain where drain current and drain voltage increase in proportion to each other, a saturation domain where drain current reaches saturation even if drain voltage increases, and a cut-off domain where, ideally, current does not flow even if drain voltage is applied. In this specification, the linear domain and the saturation domain are called ON-domains of TFT, and the cut-off domain, an OFF-domain. Also, for convenience's sake, drain current in the ON-domain is referred to as ON-current, and current in the OFF-domain as OFF-current.
The pixel matrix circuit in the active matrix liquid crystal display device is comprised of an n-channel TFT (hereinafter referred to as pixel TFT). Applied with a gate voltage of about 15 to 20 V amplitude, the TFT needs to satisfy the characteristic both in the ON-domain and the OFF-domain. On the other hand, a peripheral circuit provided to drive the pixel matrix circuit is constructed using a CMOS circuit as a base, and mainly the characteristic in the ON-domain is significant. However, the crystalline TFT has a problem in that OFF-current tends to increase. In addition, when the crystalline TFT is driven for a long period of time, degradation phenomena such as reduction in mobility and ON-current, and increase in OFF-current are often observed. One of factors of this is considered to be the hot carrier implantation phenomenon, which is caused by high electric field in the vicinity of the drain.
Lightly Doped Drain (LDD) structure is known in the LSI technical field as measure to reduce OFF-current of an MOS transistor and further to ease high electric field in the vicinity of the drain. In this structure, an impurity region with low concentration is provided between a drain region and a channel formation region, and this impurity region with low concentration is called an LDD region.
Similarly, to form the LDD structure in the crystalline TFT is known. According to the prior art, the method comprises: forming, through a first impurity element doping step, an impurity region with low concentration to be an LDD region, while using a gate electrode as a mask; forming thereafter side walls on both sides of the gate electrode, by utilizing anisotropic etching technique; and forming, through a second impurity element doping step, an impurity region with high concentration to be a source region and a drain region, while using as a mask the gate electrode and the side walls.
However, in comparison with a TFT having an ordinary structure, the LDD structure TFT may reduce OFF-current but increases series resistance component due to its makeup, resulting in undesirable decrease in ON-current of the TFT. Also, the LDD structure can not completely prevent degradation of ON-current. Known as measure to compensate these defects is the structure in which the LDD region overlaps with the gate electrode through a gate insulating film. This structure may be formed by several ways, and, for example, there are known GOLD (Gate-drain Overlapped LDD) and LATID (Large-tilt-angle implanted drain). With such structure, high electric field in the vicinity of the drain may be eased to enhance hot carrier resistance and, at the same time, decrease in ON-current can be prevented.
In the crystalline TFT also, it has been confirmed that the provision of the LDD structure improves hot carrier resistance and further adoption of the GOLD structure provides very superior effect, as compared to the crystalline TFT of a simple structure consisting of the source region, the drain region and the channel formation region (“Novel Self-aligned Gate-overlapped LDD Poly-Si TFT with High Reliability and Performance” Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97-523).
In the crystalline TFT, formation of the LDD structure is effective means to suppress hot carrier implantation phenomenon. When the GOLD structure is further employed, decrease in ON-current observed in the LDD structure can be prevented. Those structures provide good results also in terms of reliability.
Thus, structural examination of the element is required to achieve high reliability for the crystalline TFT, and formation of the GOLD structure is desirable for that point. In conventional methods, however, the LDD region may be formed in a self-alignment manner but the step of forming a side wall film by anisotropic etching is unsuited to process a large grass substrate as in the case of the liquid crystal display device. In addition, the length of the LDD region is determined by the width of the side walls, putting high limitation on degree of freedom in designing the element.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a technique to overcome those problems, and specifically to provide, through a simpler method than in the prior art, a technique of manufacturing a crystalline TFT with the structure in which a gate electrode overlaps with an LDD-region.
Though the GOLD structure may prevent degradation of ON-current, as in particularly an n-channel TFT that constitutes a pixel matrix circuit, OFF-current is sometimes increased upon application of a high gate voltage in the OFF-domain. OFF-current increases in the pixel TFT of the pixel matrix circuit, causing inconveniences such as increase in power consumption and troubled image display. This is probably because an inversion layer is formed in the LDD region formed to overlap with the gate electrode in the OFF-domain, making a passage of a hole. In that case, operation range of the TFT is narrowed and limited.
A second object of the present invention is to provide the structure for preventing increase of OFF-current in the crystalline TFT, in which a gate electrode overlaps with an LDD region, So that the operation range of the TFT may be widened, and to provide a method of making that structure.
FIGS. 17A-1
to
17
B-
4
are views schematica
Adachi Hiroki
Yamazaki Shunpei
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Lee Eddie
Ortiz Edgardo
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3045533