Apparatus and method for an error minimizing phase locked loop

Details Apparatus and method for an error minimizing phase locked loop Apparatus and method for an error minimizing phase locked loop

1999-08-17

2003-01-07

Phu, Phuong (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S341000, C714S794000

Reexamination Certificate

active

06504887

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to methods of timing recovery, and in particular to a digital phase locked loop that uses a recursive, weighted least squares algorithm to determine maximum likelihood estimates of the period and phase of an incoming signal.
BACKGROUND
Phase locked loops are used to synchronize an electronic device to a regular electrical signal. One possible form that a source signal s
ideal
can take is sinusoidal,
s
ideal
(&ohgr;,&phgr;,
t
)=sin(&ohgr;
t
+&phgr;).
If the source signal has an unknown frequency &ohgr;
s
, an unknown phase &phgr;
s
, and is corrupted by noise n(t), the phase locked loop receives an input signal s(t), where
s
(
t
)=
s
ideal
(&ohgr;
s
,&phgr;
s
,t
)+
n
(
t
).
The phase locked loop estimates the values of the frequency and the phase of the received signal to be {circumflex over (&ohgr;)} and {circumflex over (&phgr;)}, respectively. Synchronization occurs when the difference between the estimates and the true values have decreased below given tolerances &egr;
&ohgr;
and &egr;
&phgr;
:
 |&ohgr;
s
−{circumflex over (&ohgr;)}|<&egr;
&ohgr;
and |&phgr;
s
−{circumflex over (&phgr;)}|<&egr;
&phgr;
.
The phase locked loop uses the estimates {circumflex over (&ohgr;)} and {circumflex over (&phgr;)} to generate an output signal. Phase locked loops typically achieve synchronization between the input and output signals using a feedback loop comprising a phase detector, a low pass filter, and a voltage controlled oscillator. While the feedback loop converges to the true values of the frequency and phase given infinite time, the rate of convergence is often slow.
A number of phase locked loops have been designed to have an improved convergence rate. In U.S. Pat. No. 5,754,598 by Barrett, Jr. et al., modern optimal control techniques are used to control a phase locked loop for a predetermined period. Classical control techniques are used after the predetermined period. In U.S. Pat. No. 5,291,144 by Ichiyoshi, the input and output signals are complex. The output signal is multiplied by the input signal to obtain a complex phase difference, which is used as feedback to control the output signal.
U.S. Pat. No. 5,093,847 by Cheng describes an adaptive phase locked loop that has coefficients that are automatically adjusted to minimize an error signal. A purely digital approach is presented in “Efficient Digital Techniques for Implementing a Class of Fast Phase-Locked Loops” by Kobayashi et al., IEEE Transactions on Industrial Electronics, 43 (1996) pp. 616-620. In this approach, several previous measurements of the frequency of the input signal are averaged to calculate the estimated frequency {circumflex over (&ohgr;)}. However, none of the above phase locked loops are stable under large perturbations of the input signal. Furthermore, the digital approach mentioned above fails to take full advantage of modern computing power.
Finally, in U.S. Pat. No. 5,875,215 by Dobrica, a carrier synchronizing unit uses a recursive least square type phase and amplitude estimation. The synchronizing unit uses known symbol information to characterize the channel through which the input signal propagates prior to being received. However, the synchronizing unit does not lock onto the input signal directly, nor does it estimate the period of the input signal.
Furthermore, many current phase locked loops assume that the input signal is periodic. If the input signal is a digital bit stream, however, the signal is not periodic. The potential for a transition between bits occurs regularly, but a transition does not necessarily take place at every potential transition time. Present state-of-the-art systems that lock on to such aperiodic signals are not tolerant to high levels of interference and noise on the input signal.
OBJECTS AND ADVANTAGES
It is therefore a primary object of the present invention to provide a phase locked loop that converges quickly to an input signal, is robust to perturbations of the input signal, and estimates the period and phase of the input signal using purely digital means. It is an other object of the present invention to provide a phase locked loop that can lock onto a signal having periodic characteristics but which is not itself periodic.
The invention has the advantage that it provides an efficient and stable phase locked loop that can be implemented using modern integrated circuit technology. The invention has the additional advantage that it can lock onto certain noisy aperiodic signals.
SUMMARY
A method of estimating a period and a time delay of an input signal comprises the step of identifying a plurality of transition times {tilde over (t)}
i
of the input signal, where i=−(N−2) to 0. Each transition time {tilde over (t)}
i
has a corresponding weight &agr;
−i
{tilde over (&ggr;)}
i
comprising a forgetting factor a and a weighting factor {tilde over (&ggr;)}
i
. The forgetting factor &agr; reduces the importance of transition times that occurred in the past. The weighting factor {tilde over (&ggr;)}
i
gives the relative importance of transition time {tilde over (t)}
i
.
Upon receiving an N
th
transition time t
0
and an N
th
weighting factor &ggr;
0
, the period and the time delay of the input signal are estimated as {circumflex over (T)} and {circumflex over (t)}
&phgr;
, respectively. The time delay is proportional to the phase of the input signal. The values of {circumflex over (T)} and {circumflex over (t)}
&phgr;
are computed by maximum likelihood techniques using a least squares minimization of an error function that uses the weights &agr;
−i
{tilde over (&ggr;)}
i
. The estimates are made in a recursive manner, with {circumflex over (T)} depending on &agr;, &ggr;
0
, t
0
, and a preceding maximum likelihood estimate {tilde over (T)} of the period. The value of {circumflex over (t)}
&phgr;
depends on &agr;, &ggr;
0
, and t
0
.
The estimates {circumflex over (T)}and {circumflex over (t)}
&phgr;
also depend on sums
S
N
-
1
(
n
)
=
∑
i
=
-
(
N
-
2
)
0
⁢
i
n
⁢
a
-
i
⁢
γ
~
i
for n=0, 1, and 2. Specifically,
T
^
=
T
~
+
(
S
N
-
1
(
0
)
-
S
N
-
1
(
1
)
)
⁢
γ
0
a
⁡
(
S
N
-
1
(
0
)
⁢
S
N
-
1
(
2
)
-
(
S
N
-
1
(
1
)
)
2
)
+
(
S
N
-
1
(
2
)
-
2
⁢
S
N
-
1
(
1
)
+
S
N
-
1
(
0
)
)
⁢
γ
0
⁢
t
0
⁢
 
⁢
and
t
^
φ
=
-
(
S
N
-
1
(
2
)
-
2
⁢
S
N
-
1
(
1
)
+
S
N
-
1
(
0
)
)
⁢
γ
0
a
⁡
(
S
N
-
1
(
0
)
⁢
S
N
-
1
(
2
)
-
(
S
N
-
1
(
1
)
)
2
)
+
(
S
N
-
1
(
2
)
-
2
⁢
S
N
-
1
(
1
)
+
S
N
-
1
(
0
)
)
⁢
γ
0
⁢
t
0
.
Once {circumflex over (T)} and {circumflex over (t)}
&phgr;
are obtained, the sums are updated in preparation for a subsequent estimate of the period and time delay.
The present method is preferably implemented by an integrated circuit that produces an output signal whose period and time delay are equal to {circumflex over (T)} and {circumflex over (t)}
&phgr;
, respectively. The physical implementation of the present method therefore results in a digital phase locked loop.
In some embodiments, the forgetting factor &agr;=1. In some embodiments, the weighting factors &ggr;
i
=1. In the preferred embodiment, &agr;<1, and each of the weighting factors &ggr;
i
is given a value indicating a confidence level in the accuracy of transition time t
i.
The weighting factors are particularly useful when receiving a signal with absent transitions. A weighting factor of zero is assigned to missed transitions; therefore good estimates of the period and time delay are maintained. Thus the digital phase locked loop of the present invention can lock onto some aperiodic signals.
The forgetting factor &agr; is adjusted to give a desired insensitivity to noise. As &agr; approaches 1, the estimates {circumflex over (T)} and {circumflex over (t)}
&phgr;
of the period and time delay become increasingly unresponsive to noise as well as to long-term changes in the period and time delay of the input signal. The f

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