Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-07
2003-09-09
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257S330000, C257S364000, C257S407000
Reexamination Certificate
active
06617632
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a manufacturing technology therefor, and particularly to a technology effective for application to a nonvolatile memory semiconductor device having electrically erasable programmable parallel connection-type nonvolatile memory cells.
BACKGROUND OF THE INVENTION
In a nonvolatile memory semiconductor device, nonvolatile memories capable of electrically writing data therein and erasing the same therefrom are able to rewrite or update data in a state of being built onto a wiring board, for example and are easy to use. Therefore, they have widely been used in various products that need the memories.
In particular, an electrical batch erasure-type EEPROM (Electric Erasable Programmable Read Only Memory: hereinafter called a “Flash memory”) has the function of collectively electrically erasing data lying in a predetermined range (including all the memory cells or a predetermined memory cell group in a memory array) of the memory array. Further, since the flash memory has a one-transistor stacked gate structure, the downscaling of each cell is put forward and expectations on high integration thereof are also high.
In the one-transistor stacked gate structure, one nonvolatile memory cell (hereinafter abbreviated simply as “memory cell”) basically comprises one two-layer gate MISFET (Metal Insulator Semiconductor Field Effect Transistor). The two-layer gate MISFET is formed by providing a floating gate electrode on a semiconductor substrate with a tunnel oxide film interposed therebetween and stacking a control gate electrode thereon with an interlayer film interposed therebetween.
The storage of data in the flash memory is carried out by injecting electrons into the floating gate electrode or pulling out or extracting the electrons from the floating gate electrode. For example, a NOR type flash memory typified by a parallel connection-type nonvolatile memory carries out data processing in the following manner.
In order to perform the writing of data, a source region and a substrate are grounded and a relatively high voltage is applied to a control gate electrode and a drain region. Thus, electrons move or travel on a channel region near the surface of the substrate from the source region to the drain region at high speed, and electrons each having obtained sufficiently high energy in the neighborhood of the drain region in which the channel region is pinched-off, result in hot electrons. The hot electrons are capable of jumping over a potential barrier of a gate insulating film placed under a floating gate electrode. Owing to an electric field produced by the control gate electrode, the hot electrons get over the barrier of energy and are attracted to and injected into the floating gate electrode. This injection is normally called “hot electron injection” or “channel injection”. In the present specification, it will hereinafter be called “HE injection”. By doing so, the floating gate electrode is negatively charged and the threshold value as viewed from the control gate electrode becomes higher than a predetermined value. This state in which the threshold voltage is higher than the predetermined value, is called a “data-written state”, e.g., a logic “0”.
Further, FN tunneling (Fowler-Nordheim tunneling) of the thin gate insulating film placed below the floating gate electrode carries out the erasing of data. When, for example, a relatively high voltage is applied to the control gate electrode in a state in which the source and drain regions are open, electrons lying in the floating gate electrode are pulled out to the semiconductor substrate placed under the floating gate electrode (tunnel emission), and the potential at the floating gate electrode is returned to neutrality, so that the threshold voltage as viewed from the control gate electrode becomes lower than a predetermined value. This state in which the threshold voltage is lower than the predetermined value, is called a “data-erased state”, e.g., a logic “1”. The FN tunneling can be effected even on a semiconductor region for the source region or drain region located under the floating gate electrode except for the substrate.
Furthermore, in order to carry out the reading of data, a voltage, which ranges from about 3 V to about 5 V, for example, is applied to the control gate electrode. Since, at this time, no current flows in a channel region in the case of a memory cell with data written therein but a current flows in a channel region in the case of a memory cell with data erased therefrom, the logics “1” and “S” can be distinguished from each other, and hence information can be read from the memory cell.
In an actual memory cell array, a plurality of word lines extending in a row direction and a plurality of bit lines extending in a column direction are placed so as to intersect one another. Memory cells are respectively disposed at points where the word lines and the bit lines intersect. The drain regions of the respective memory cells are connected to their corresponding bit lines, and the source regions of the respective memory cells are connected to their corresponding source lines. Thus, when data is written into the corresponding memory cell, both a word line (hereinafter called a “selected word line”) and a bit line intended for writing are respectively set to a relatively high voltage. When data is erased from the corresponding memory cell, a selected word line may be set to a relatively high voltage in a state in which a bit line and a source line are open. Such a parallel connection-type nonvolatile memory semiconductor device has been described in U.S. Pat. No. 4,868,619.
Incidentally, while the high integration of the flash memory is put forward on the strength of the progress of extensive technologies such as a micro-fabrication technology, a new circuit technology or a downsized package technology, etc., various problems incident to the scale-down or downsizing of each memory cell arise. Even as to this, however, the scale-down of each memory cell is realized while achieving an improvement in memory cell structure, a change in operating voltage, etc.
For example, in the flash memory having the cell layout of NOR type, which corresponds to one parallel connection type discussed by the present inventors, a problem has been clarified in that upon a punch-through phenomenon due to a short channel effect in the main, and writing, an increase in leak current developed in each memory cell (hereinafter called “non-selected memory cell”) unintended for writing, which is connected to each memory cell (hereinafter called “selected memory cell”) intended for writing with a bit line shared therebetween will reduce the reliability of the flash memory.
As for the short channel effect, however, an n type semiconductor region, which constitutes a drain region, is surrounded by a punch-through stopper layer indicative of p type conductivity to allow the prevention of punch-through. Namely, the major cause of the short channel effect resides in that a depletion layer developed from the drain region of each memory cell reaches the source region and a current flows between the source and drain regions. However, the suppression of the extension of the depletion layer produced from the drain region by the punch-through stopper layer allows the avoidance of the generation of the short channel effect even if a gate length is about 0.3 &mgr;m.
A method of applying a negative voltage to a word line (hereinafter called “non-selected word line”) unintended for writing has been adopted to cope with the increase in the leak current developed in the non-selected memory cell. It is thus possible to control or suppress the leak current developed in each non-selected memory cell having a drain region to which a voltage is applied upon writing. Incidentally, for example, Unexamined Patent Publication No. Hei 5(1993)-182473 has been disclosed as an example of the Patent which has described a flash memory wherein a leak blocking voltage is applied to a non-selected word li
Kume Hitoshi
Matsuzaki Nozomu
Shiba Kazuyoshi
Shukuri Shoji
Takada Hidenori
Hitachi , Ltd.
Miles & Stockbridge P.C.
Nelms David
Tran Mai-Huong
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